10 Commits

Author	SHA1	Message	Date
Keerthan Jaic	67e323bdfa	Added *egg-info/ ... --HG-- branch : mep107	2013-07-06 17:54:01 -04:00
Jan Decaluwe	20a9394123	break up the modeling chapter in three ... Mark high level clearly as separate from synthesis --HG-- branch : 0.8-dev	2012-05-06 09:59:31 +02:00
Jan Decaluwe	71123d8996	vsim intro	2010-09-11 23:15:09 +02:00
Jan Decaluwe	1a438778b9	introduced vsim as unit test simulator (both with vlog and vcom)	2010-09-11 23:08:51 +02:00
Jan Decaluwe	4cad5a171e	Support for conversion of ternary operator. ... They are converted to ternary equivalents in the target HDL. If possible, they are converted to single line assigns. Within a process, this will only work with VHDL-2008.	2010-07-01 19:13:42 +02:00
Jan Decaluwe	1697a4fab0	prepare for development release	2008-08-21 15:29:10 +02:00
traber@win.desy.de	4c54ab4b1e	print with more than one argument does not raise an error anymore but creates a warning.	2008-07-22 14:14:30 +02:00
thomas.traber@desy.de	40d425d305	Avoid Array Error	2008-07-22 09:48:45 +02:00
Jan Decaluwe	61d779e738	ignore patterns	2008-06-16 20:38:11 +02:00
Jan Decaluwe	1515f3cad8	ignore patterns	2008-05-28 14:28:29 +02:00