* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default
2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py
This needed the changes of 1) above.
* 1) _Signal.py
added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ...
added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)`
2) _block.py
minor changes
3)_hdlclass.py
removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present
cleaned the code to what is actually working
4) _traceSignals.py
The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting.
So reworked this file to skip adding the None-level
Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice.
Introduce f'strings
5) _analyze.py
changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always
6) test_xxxx.py
changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword
* cleaned test/bugs
replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords
* replacing more occurrences of *logic* by either *comb* or *synch*
* one *comb* too many :(
* added small test_hdlclass0.py to help in debugging
updated the 'doc' section -- needs publishing
added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
This change does exactly what the 'directory' attribute for toVerilog and toVHDL
do. It allows the user to specify the output directory for VCD files.
This commit includes the source change, documentation change, and a py.test
change to test the functionality.
Updated the MyHDL manual to include the 0.9 what's new in the
index and additional verbage in the conversion section on
interfaces. This commit is also being used as a test vehicle
for the new development flow using git.
