* Update ci flow to track with changes for ghdl-ci, #449
* Fix to address ghdl issue on windows
* Update full flow to ghdl/setup-ghdl@v1 and remove local build of ghdl
* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default
2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py
This needed the changes of 1) above.
* 1) _Signal.py
added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ...
added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)`
2) _block.py
minor changes
3)_hdlclass.py
removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present
cleaned the code to what is actually working
4) _traceSignals.py
The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting.
So reworked this file to skip adding the None-level
Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice.
Introduce f'strings
5) _analyze.py
changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always
6) test_xxxx.py
changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword
* cleaned test/bugs
replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords
* replacing more occurrences of *logic* by either *comb* or *synch*
* one *comb* too many :(
* added small test_hdlclass0.py to help in debugging
updated the 'doc' section -- needs publishing
added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
* Removed support for Python 3.7 (which is End Of Life since 2023-06-27)
Removed stray ast.Str and the like , which throw deprecation warnings in Python 3.12
* corrected import pathj for raises_kind
* corrected `ord` value assignemnt in _toVerilog.py
removed forgotten ast.dump call from _analyze.py
* Added `OpenPort` to emulate VHDL 'open' port
* Of course we need the new module: _openport.py
* refining detection of OpenPrt in _toVerilog.py
* Corrected constant array for Verilog 2005
* Added `Constant` signal object
* Corrected *_shortversion*
ToDo: replace by single global variable in myhdl/myhdl/__init__.py
* one more *_shortversion* ...
* Cleaning up tests:
removing wildcard imports
correcting indents
remving as much warnings as possible: mostly unused variables
* TestInferWaiter: correct mismatch in number of arguments
* replacing `for __` inside generator with `for dummy`
cleaning ud 'bugs' section too
* repaired some over-optimistic "Verschlimmbesserungen"
* some more repairs of new *Vershlimwbesserungen* - literally *improvements that make things worse* :)
* Updating README.md to show alternative solutions to insatll MyHDL instead of installing from the *lagging* PyPI
* removing *stale* link to Travis CI build status; need to find build status of GitHub Actions?
updating link to Discourse
* getting Discourse image from third-party web-site
* replacing thirdparty Discourse image by original version from Discourse web-site
* trying to make the Discourse a bit smaller
* second try to change the image size
* third try
* reformatting positions of *badges*
* still reformatting ...
* trying harder
* adding empty lines after *badges*
* editing text
* Add initial actions for winows, include core and ghdl, iverilog is not working yet
* Rename some steps to show linux providence
* Rename some steps to show linux providence
* Add initial support for match/case in python, only available in 3.10 on
* Fixed testing so that only the match code is used on python 3.10 or above
* Add spport for enumerated types in match statments
* Rewrote the code to leverage the correct AST way of walking the case/match tree to build the correct RTL versions
* Removed enumerate where not used
* Removed enumerate where not used
* Move appropriate code into match_case definition
* Remove unused defs
* Remove unused defs
* Cleanup of redundant code, and replace some simple variable names with more representative names
* Add test for the inverting of a constant integer (~0x3, ~0x24 etc), this works in myhdl and verilog but fails in VHDL
* In the cases where the value being inverted is a constant, calculate in the conversion stage the correct inversion value and store that, for a not on a signal name or a boolean there is no change
* Rewrite code so that a not int looks like a not int in the VHDL and not the calculated result
* Ignore the warning as it is a operational message not a testing message
* Change ast.Constant to ast.Num, the latter was only introduced in python3.8, it will be deprecated
* Rewrite code to be python version dependent, ast.Num was removed in favour of ast.Constant in 3.8
* Add tests that shows failing case, in VHDL. When many unsigned, single bit signals are BinOped together (Or'ed in this case) to a boolean (std_logic). Verilog works
* Remove clk from design where it is not used
* Update tests to find more corner cases
* Add dest to rhs signal to allow the destination signal to be rippled along the chain if there are multiple elements/signals being assigned
* Move conditional so the whole job doesn't run unless it is a tag
* Add dist to make and restructure release
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add README to release to appear on PyPi
* Added read definition
* Clean up verify convert warnings
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Fixed all tests to handle the analyze/verify deprecation
* Fixed to catch the correct error, List of signals as a port is not supported
* Add a way to search for and add myhdl.vpi
* Add explict test to check for deprecation case
* Change warning from UserWarning (which is the default) to DeprecationWarning
* Change test operation from script to makefile
* No longer use travis
* Add some ANSI colored logging
* Fixed test to look for DeprecationWarning
* Add lining step
* Add linting step
* Add linting step
* Remove matrix step
* Add work/ to clean list
* Hide echo commands in window
* The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks
* Add myhdl.vpi to clean
* Mark these tests as xfail, for now,
* Fix and unmark xfail 2 tests
* Add black support
* Remove python2 only testing
* Need to relook at this test, it performs differently for verilog and vhdl
* Add RTL files to the list
* Need to relook at this test, it performs differently for verilog and vhdl
* Upgrade to DeprecationWarnings
* Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged
* Add more examples for the Deprecation cases, toVHDL and toVerilog
* Fix deprecations catching
* Fix pytest to use pytest.ini
* Add pypi release steps
* Fix intbv error
* Fix indent
* Update to do a release
* Add checkout to step
* Update Python versions
* Add dependancy on tag on push
* _ShadowSignal.py: conversion:
enabled taking a ShadowSignal of a ShadowSignal,
reworked _setName() to aggregate chained slicing/indexing to a single slice or index
marked the shadowed Signal as always 'read'
_intbv.py: added the [n:] to __repr__
_toVHDL.py: added a comment
* added test for recursive/chained ShadowSignals
* added missing returned instance
* wrong startvalue
* Changed a docstring to launch GitHub actions on origin
* [ENH] Updated the ConcatSignal conversion code to check for undriven signals.
* [ENH] Added a test to check the undriven ConcatSignal converts sensibly.
* First working yml for github actions
* Remove redundant lines
* Test with building ghdl from source
* Re-enable all versions of python
* Re-enable all versions of python
* python-3.11 not available yet
* Add weekly cron on Sunday
Co-authored-by: Douglas Kastle <douglas.kastle@gmail.com>
* palce xfail on rename_after ... test
* Adding a commmnet to force commit
* alternate approach in testOBufInterface
* reverting _analyze.py
reaming the simulation objects
* typos
* final commit to 'finish' PR submission
* And of course I forgot the 'xfail'
* cleaning up wild import in test_tristate.py to provoke another Travis/CI run
* There is something wrong with the 'xfail' so I just commented out the offender
* uncommented the second test in test_tristate.py
* Changed the object names in the testbench, hoping to narrow down where it fails
* Changing more object names
* myhdl.c: added #ifdef _WIN32 clause to get the pipes working in WIndows 10, properly (auto-)formatted the source
util.py: changed the myhdl.vpi path to defaukt to iverilog's known system path
test_tristate.py: the TestTristate class re-used the tristate_obuf.o for the test with the interface; which put iverilog on the wrong foot ...
* util.py: make a distinction between Windows and Linux systems where to get myhdl.vpi
