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Author SHA1 Message Date
jandecaluwe
1f960db066 Merge pull request #144 from nicmcd/master 
Add 'directory' attribute to traceSignals.
 2016-01-26 16:38:20 +01:00
Nic McDonald
94bc28f076 Add 'directory' attribute to traceSignals. 
This change does exactly what the 'directory' attribute for toVerilog and toVHDL
do. It allows the user to specify the output directory for VCD files.

This commit includes the source change, documentation change, and a py.test
change to test the functionality.
 2016-01-24 22:17:37 -08:00
jandecaluwe
fb70bb2fc4 Merge pull request #137 from nturley/master 
fix bug in test_custom tests
 2015-11-29 11:51:19 +01:00
jandecaluwe
480d228236 Merge pull request #135 from nturley/patch-1 
add test for issue 134
 2015-11-29 11:47:59 +01:00
nturley
bb2ba3c954 fix bug in test_custom tests 2015-11-15 23:50:34 -06:00
nturley
d60568ae65 fix additional issues with test_issue134 
we only need to analyze. Verify will still fail even with the fix
 2015-11-07 22:21:50 -06:00
nturley
8cc5f23dcb fix test 134 
wrong number and add xfail
 2015-11-07 21:53:35 -06:00
nturley
ed9d2a9e90 add test for issue 134 
checks for port name collision when a function names two signals with the same name
 2015-11-07 21:08:38 -06:00
Jan Decaluwe
9dffa04130 Merge branch '0.9-maintenance' 2015-11-01 21:02:07 +01:00
jandecaluwe
b726eb8139 Merge pull request #133 from clade/0.9-maintenance 
assign statement (constwires) support litterals larger than 32 bits
 2015-11-01 20:59:29 +01:00
Jan Decaluwe
65e6355e11 Added parenthesis to print 2015-11-01 20:32:19 +01:00
Jan Decaluwe
97c8c8ac7d Improve on large constant wires in VHDL 
Triggered by an reported issue with Verilog that
I was not able to reproduce (issue 133).
 2015-10-30 20:38:33 +01:00
Pierre Cladé
ff5b0b1963 assign statement (constwires) support litterals larger than 32 bits 2015-10-29 19:03:14 +01:00
Jan Decaluwe
97dd4e3767 Remove allowed failures 2015-10-25 16:54:08 +01:00
Jan Decaluwe
cb06b1eb88 Remove broken tests - revisit writing to file in conversion later 2015-10-25 16:45:10 +01:00
Jan Decaluwe
69a0e2e5ef Really test function without return value 2015-10-25 16:33:28 +01:00
Jan Decaluwe
107e0e0c1e Return intbv instead of an intbv subclass for certain methods 
In this way, no requirement is implicitly assumed for the
interface of the subclass.
 2015-10-25 15:39:17 +01:00
Jan Decaluwe
385e82dd7e Support negative values in ConcatSignal contributors 2015-10-10 20:20:29 +02:00
jandecaluwe
bd0cfba9a7 Merge pull request #130 from jck/py35 
Python 3 fixes, test improvements
 2015-10-07 20:23:12 +02:00
jandecaluwe
ddcc815fd7 Merge pull request #129 from jck/symbols 
always_seq, always_comb improvements
 2015-10-07 20:18:42 +02:00
Keerthan Jaic
ba99b90660 ignore some py2 specific tests on py3 2015-10-02 23:52:23 -04:00
Keerthan Jaic
1f62e0200c test_cosim: don't import helpers while running directly 2015-10-02 23:21:57 -04:00
Keerthan Jaic
a0256decaf move raises_kind to test/helpers.py 
This allows us to use raises_kind from all tests
 2015-10-02 23:21:54 -04:00
Keerthan Jaic
8ec646417d test/conv/toVerilog: use relative imports 
Use relative imports for the local files such as util.py
 2015-10-02 23:21:23 -04:00
Keerthan Jaic
de8b4d4925 add __init__.py to test subfolders 
Since we have multiple tests with the same filename, we need __init__.py
in the subfolders to allow py.test to differentiate between them.
 2015-10-02 23:21:19 -04:00
Keerthan Jaic
a6f2d54e83 remove __init__.py from top level test folder 
https://pytest.org/latest/goodpractises.html
It is advised to avoid __init__.py in the top level test folder in
order to easily run tests against an installed package version.
 2015-10-02 23:21:15 -04:00
Keerthan Jaic
8335818c4d use print functions in conversion tests 2015-10-02 22:14:51 -04:00
Keerthan Jaic
8a4fd65558 test_RandomScrambler: fix range() call for py3 2015-10-02 22:14:44 -04:00
Keerthan Jaic
1664847130 add __int__ magic method to EnumType 2015-10-02 22:14:42 -04:00
Keerthan Jaic
cb2332a37d test_hec: remove L suffix 2015-10-02 22:14:39 -04:00
Keerthan Jaic
426786aabf handle ast.Try in py3 2015-10-02 21:27:47 -04:00
Keerthan Jaic
2172cbfd91 fix visit_Call for python 3.5 
fixes #131
 2015-10-02 20:04:05 -04:00
Keerthan Jaic
5c9b9e1866 simplify freevar computation 2015-10-02 17:39:02 -04:00
Keerthan Jaic
0f8436bd99 compute symdict in _Always class initializer 
This code was previously repeated in the AlwaysSeq and AlwaysComb
classes.
 2015-10-02 17:36:44 -04:00
Keerthan Jaic
416e7e9ced travis: add python 3.5 2015-10-02 16:27:11 -04:00
Keerthan Jaic
764f7007ba replace _cell_deref hack with cell_contents 2015-10-02 16:23:53 -04:00
Jan Decaluwe
0bc41cc0f3 Fix #127 
Lookup cellvars in a more direct way
 2015-09-27 21:44:48 +02:00
Jan Decaluwe
beed676d4b Fix #122 by removing support for named constant in VHDL 2015-09-26 15:43:53 +02:00
Jan Decaluwe
f10eb6d3d2 Remove doubtful support for lenStr 2015-09-26 13:53:23 +02:00
Jan Decaluwe
b28ef3e2da Fix #122 2015-09-26 13:20:45 +02:00
Jan Decaluwe
381f6e396c Add cast infer 2015-09-19 12:24:42 +02:00
Jan Decaluwe
68ac94cc54 Fix #114 2015-09-18 20:46:48 +02:00
jandecaluwe
97f9b3479b Merge pull request #119 from josyb/GroupMemSignalsinVCD 
[enhancement] added scope-module// upscope around mem signals in.vcd
 2015-08-07 22:14:15 +02:00
Josy Boelen
3c8733b0df added scope-module// upscope around mem signals to properly display in a group with Impulse plugin (http://toem.de/) for Eclipse 2015-08-01 14:22:03 +02:00
jandecaluwe
fdc453fcc7 Merge pull request #118 from cfelton/concat_issue_117 
fixed bool const concat bug and added test
 2015-07-30 22:53:03 +02:00
Christopher Felton
d24c465dae fixed bool const concat bug and added test 2015-07-28 11:25:02 -05:00
jandecaluwe
0f106505cb Merge pull request #116 from jck/signamevisitor 
prevent adding intbv to senslist of always_comb
 2015-07-28 14:25:21 +02:00
jandecaluwe
c7d92c471c Merge pull request #115 from cfelton/verilog_inout 
Added inout pot declaration to Verilog conversion for TristateSignals
 2015-07-28 14:23:43 +02:00
Keerthan Jaic
443024ff29 prevent adding intbv to senslist of always_comb 
Since the merging of always_comb and always_seq NodeVisitors in #113,
intbvs are also added to the inputs by SigNameVisitor(in addition to
sigs and listofsigs). Since always_comb assumed that only sigs and
listofsigs are present in inputs, it wrongly addded intbvs to the
sensitivity list.
 2015-07-28 01:57:33 -04:00
Christopher Felton
16bbf7e960 Merge branch 'master' of https://github.com/jandecaluwe/myhdl into verilog_inout 2015-07-27 11:31:50 -05:00