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Author SHA1 Message Date
Jan Decaluwe
a0010c904a moved ShadowSignal classes to separate module 2009-06-11 19:18:45 +02:00
Jan Decaluwe
6a280b0767 generalized shadow signal, created _SliceSignal subclass 2009-06-09 18:33:55 +02:00
Jan Decaluwe
cab4c4be8b Turned Signal into a factory function, renamed class to _Signal 2009-06-09 18:07:38 +02:00
Jan Decaluwe
50b2877124 First pass on shadow signals 2009-06-09 17:22:50 +02:00
Jan Decaluwe
3ee96baf1f Merge from 0.6-maint 2009-05-10 08:11:23 +02:00
Jan Decaluwe
8a9ab6cc57 fixed typo 
--HG--
branch : 0.6-maint
 2009-05-10 08:09:10 +02:00
Jan Decaluwe
dc10d0899d COMPLETED - move to ast 
All conversion unit tests work.
 2009-05-09 08:41:59 +02:00
Jan Decaluwe
c1e31def1e UNSTABLE - move to ast 
test_dec.py works
 2009-05-08 21:58:49 +02:00
Jan Decaluwe
7bacfd9c9e UNSTABLE - move to ast 
test_bin2gray works
 2009-05-08 20:22:48 +02:00
Jan Decaluwe
d7c142ad18 UNSTABLE - move to ast 
test_hec.py works for VHDL
 2009-05-04 18:08:57 +02:00
Jan Decaluwe
cad761f30d UNSTABLE - replace compiler by ast 
All unit tests for Verilog conversion work.
 2009-05-03 10:38:52 +02:00
Jan Decaluwe
e6ba8d4ec1 UNSTABLE - replace compiler by ast for conversion 
Tests in conversion/general for Verilog work.
 2009-05-02 22:51:08 +02:00
Jan Decaluwe
c962b8542e UNSTABLE - replace compiler by ast in conversion package 
test_hec.py works for Verilog
 2009-05-02 08:41:32 +02:00
Jan Decaluwe
3d656fd49a Use ast package instead of compiler 2009-04-27 19:26:12 +02:00
Jan Decaluwe
e3cb33b029 Use new standard function for generator function check. 2009-04-26 18:10:37 +02:00
Jan Decaluwe
9e416df6ff Replaced compiler by ast 2009-04-26 18:03:43 +02:00
Jan Decaluwe
cb2ddfb596 merge from 0.6-maint 2009-04-25 21:01:16 +02:00
Jan Decaluwe
2b7f4696de Check for "augmented signal assignemnt" (unsupported). 
This has no semantic equivalence in Verilog/VHDL

--HG--
branch : 0.6-maint
 2009-04-25 20:56:47 +02:00
Jan Decaluwe
fc227fa570 Merge from 0.6-maint 2009-04-25 19:54:17 +02:00
Jan Decaluwe
3cf551cb65 Removed decprecated Set module import. 
On some places, the built-in set type was not yet used

--HG--
branch : 0.6-maint
 2009-04-25 19:49:04 +02:00
Jan Decaluwe
75d85e4b98 setup 0.7dev in default branch 2009-04-25 16:51:01 +02:00
Jan Decaluwe
b2f01c17e0 start 0.6 maintenance branch 
--HG--
branch : 0.6-maint
 2009-04-25 16:47:16 +02:00
Jan Decaluwe
6eb53a6913 Added tag 0.6 for changeset 9e45b91ac223 2009-04-25 16:42:29 +02:00
Jan Decaluwe
f2877dac31 merge 2009-01-09 22:18:50 +01:00
Guenter Dannoritzer
ac26dda8a5 Fixed two typos, added an intbv class link and reformated an paragraph 2009-01-09 18:07:35 +01:00
Jan Decaluwe
ec8a033ff5 Added tag rel_0-6 for changeset 9e45b91ac223 2009-01-09 15:01:42 +01:00
Jan Decaluwe
cfcb456e53 corrected whatsnew link 0.6 rel_0-6 2009-01-09 13:24:09 +01:00
Jan Decaluwe
653e8ae511 small doc fixes 2009-01-09 12:33:14 +01:00
Jan Decaluwe
63b8f09a70 fixed return value of len() in doc 2009-01-08 15:54:08 +01:00
Jan Decaluwe
48d3aeb80f merge 2009-01-08 15:44:16 +01:00
Jan Decaluwe
f65fee6f5e proofread and restructuring of intbv documentation 2009-01-08 15:36:32 +01:00
Jan Decaluwe
96a11d0eea fixed bug in Verilog conversion of 'ord' function 2009-01-05 16:37:43 +01:00
Jan Decaluwe
3c0148c6bf merge 2009-01-05 16:11:51 +01:00
Jan Decaluwe
5bb4dc4ec0 solved bug in VHDL conversion of functions 2009-01-05 16:08:38 +01:00
Jan Decaluwe
46162e8823 minor doc fixes 2008-12-22 18:19:57 +01:00
Jan Decaluwe
7255653ed2 version number 0.6 2008-12-21 15:42:55 +01:00
Jan Decaluwe
20fd41d5fe check whether intbv call argument is constant 2008-12-12 22:48:43 +01:00
Guenter Dannoritzer
515265773a Fixed typos in the manual 2008-12-09 13:42:22 +01:00
Guenter Dannoritzer
df3b5d5c54 Added another index entry for intbv conversion 2008-12-09 12:50:31 +01:00
Guenter Dannoritzer
d3929bea20 Added index entry to intbv conversion documentation 2008-12-09 12:39:06 +01:00
Guenter Dannoritzer
e6ac4e8bef Added examples of intbv instantiation 
Added some examples about creating intbv instances in the subsection
"Bit oriented operations" of the manual.
Did some small rewording in the bit slicing subsection.
 2008-12-09 12:12:34 +01:00
Guenter Dannoritzer
75c474bfea Fixed small formating error in the signed() section 2008-12-05 15:49:50 +01:00
Jan Decaluwe
fbf38849ea Solve some VHDL conversion bugs from filter project 2008-12-04 11:25:29 +01:00
Jan Decaluwe
eaafdaa33f Added tag rel_0-6dev10 for changeset 15b58c07d987 2008-12-02 11:20:58 +01:00
Jan Decaluwe
8b8d6cf206 Removed tag rel_0-6dev10 rel_0-6dev10 2008-12-02 11:13:11 +01:00
Jan Decaluwe
0e6dfe8f48 Merge 2008-12-02 11:12:37 +01:00
Jan Decaluwe
c75b08532f Added tag rel_0-6dev10 for changeset 5e746c91ea7a 2008-12-02 11:08:22 +01:00
Jan Decaluwe
ce3e8c00b2 Updated copyright notice, removed keyword expansion symbols 2008-12-02 11:08:08 +01:00
Jan Decaluwe
141c10fcae Added missing test file 2008-12-01 23:01:53 +01:00
Jan Decaluwe
10c39e9790 Added intbv.signed conversion test based on core test. 
This test includes slices and concats. Some issues came up that
required further changes to the convertor code.
 2008-12-01 17:15:21 +01:00