FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
1,830 Commits 9 Branches 41 Tags
Commit Graph

1830 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Isaac Garzon
d3b17a56f2 Refactored set_inheritance code into the _util module 
Fixed the VPI tests for Windows
 2015-06-28 20:36:09 +03:00
Keerthan Jaic
91a8148953 docs: Move old whatsnew to separate section 2015-06-27 08:47:55 -04:00
Keerthan Jaic
3b78a68981 docs: use version from myhdl.__version__ 2015-06-27 08:43:37 -04:00
Keerthan Jaic
ebb1b12ff8 whatsnew update 2015-06-27 08:36:23 -04:00
Keerthan Jaic
0253256938 Fix newlines in whatsnew/0.4.rst 2015-06-27 08:14:05 -04:00
Keerthan Jaic
c8ed68d148 workaround unrelated bug in test_interfaces4 2015-06-27 07:43:12 -04:00
Keerthan Jaic
87fd17be79 test/core: some whitespace lint fixes 2015-06-27 05:27:53 -04:00
Keerthan Jaic
ce89c6a1b6 test/core: cleanup unused imports 2015-06-27 05:17:07 -04:00
Keerthan Jaic
af42ad7ecf refactor frequenty used exception kind check pattern 2015-06-27 04:58:57 -04:00
Keerthan Jaic
e0b4690f48 test_intbv: simplify some tests using pytest.raises 2015-06-27 04:58:31 -04:00
Keerthan Jaic
168b0670c4 test_modbv: simplify some tests using pytest.raises 2015-06-27 04:39:33 -04:00
Keerthan Jaic
d7869ddf6e test_enum: simplify some tests using pytest.raises 2015-06-27 04:36:01 -04:00
Keerthan Jaic
3883e037ca test_Signal: simplify some tests using pytest.raises 2015-06-27 04:33:35 -04:00
Keerthan Jaic
39bf329fa7 remove unittest main in core tests 2015-06-27 03:46:16 -04:00
Isaac Garzon
e8def55da7 Removed python < 3.4 support code from cosimulation 
Separated Windows and Linux ModelSim VPI code
 2015-06-26 11:10:20 +03:00
Isaac Garzon
44007d4658 Fixed python indentation... 2015-06-26 03:53:13 +03:00
Isaac Garzon
329d7a1785 Windows support for co-simulation 2015-06-26 03:24:18 +03:00
Keerthan Jaic
b4d2b8a48b renable pypy cosimulation tests 2015-06-24 22:35:05 -04:00
Keerthan Jaic
d25274b0d8 Fix cosim test for pytest 2015-06-24 16:15:20 -04:00
Keerthan Jaic
f750688630 test_signal: rename setup, teardown for pytest 2015-06-24 16:14:50 -04:00
Keerthan Jaic
6da1f50b85 Create tmpfile fixture for tracesignals test 
This ensures that the generated VCDs don't  clutter the project tree,
and allows us to do parallel testing using pytest-xdist.
 2015-06-24 16:12:56 -04:00
Keerthan Jaic
4e13aa1daa Convert most core unittests to pytest 
These tests can be directly converted now since they don't use
setup/teardowns
 2015-06-24 15:58:15 -04:00
Keerthan Jaic
758e172f92 tox: install pytest-xdist, set pytest basetemp dir 2015-06-24 13:04:23 -04:00
Keerthan Jaic
8f70de0895 change core test assertions to pytest style 2015-06-24 13:04:07 -04:00
Keerthan Jaic
3adb53a046 test_cosim: use abspath in the exe 
This ensures that this test will run from anywhere instead of just
test/core.
tox now works for all core tests
 2015-06-24 11:20:10 -04:00
Keerthan Jaic
cdf2b1aa68 move perf_inferwaiter to benchmarks dir 2015-06-24 11:20:10 -04:00
Keerthan Jaic
7fea7bdd9d avoid renaming attribute references twice 
This commit fixes bugs introduced by 08519b4
Fixes #82
 2015-06-23 05:57:14 -04:00
Keerthan Jaic
2a08b7d60c wip: whatsnew update 2015-06-22 06:51:00 -04:00
jandecaluwe
254e458917 Merge pull request #87 from josyb/std_logic_ports-ShadowSignals 
std_logic_ports and ShadowSignals (revisited)
 2015-05-31 14:52:58 +02:00
jandecaluwe
47522facc3 Merge pull request #85 from cfelton/test_interfaces 
fixed convertible testbench issues
 2015-05-31 10:35:45 +02:00
Christopher Felton
5a2e113b07 fixed convertible testbench issues 2015-05-30 08:50:09 -05:00
Josy Boelen
06f1e208f4 added the (instructed) code to rename ShadowSignals of std_logic_ports 2015-05-30 10:58:09 +02:00
jandecaluwe
846f7ad444 Merge pull request #83 from cfelton/test_interfaces 
Added test for issue #82
 2015-05-28 19:40:53 +02:00
Christopher Felton
9c33b91292 removed unused import and change to convertible print format 2015-05-27 21:44:42 -05:00
Christopher Felton
39098a3193 added test for issue #82 2015-05-27 21:27:30 -05:00
Jan Decaluwe
06be75b9b4 Remove toVHDL.numeric_ports 2015-05-25 22:18:24 +02:00
jandecaluwe
dc1deff069 Merge pull request #80 from josyb/ConcatSignal-constant-intbv-width-of-1 
ConcatSignal
 2015-05-25 18:43:47 +02:00
Josy Boelen
e9b78d6647 removed _numeric check 2015-05-25 18:38:45 +02:00
Josy Boelen
84712ab7f2 ConcatSignal: added support for intbv with width of 1, added cast to unsigned if Signal is a port of type std_logic_vector 2015-05-25 15:37:12 +02:00
Jan Decaluwe
f4e1b996c9 Propose better solution for std_logic ports 2015-05-25 13:39:28 +02:00
Jan Decaluwe
d38a452ae6 Fix 'long' compatiblity 2015-05-23 22:48:02 +02:00
Jan Decaluwe
082847ee3a a test for the fix 2015-05-23 22:15:08 +02:00
Jan Decaluwe
ea48e0f049 Merge branch 'josyb-ConcatSignal_with_constants' 2015-05-23 22:13:47 +02:00
Josy Boelen
b7050d3b14 Update _ShadowSignal.py 
removed dangling ']' in toVerilog()
 2015-05-23 16:19:00 +02:00
Josy Boelen
9287256714 replaced call to buitl-in 'bin'function with call to 'bin function from _bin.py 2015-05-23 14:38:16 +02:00
Jan Decaluwe
33943723b8 Support for conversion of constants in ConcatSignal interface 2015-05-23 03:59:19 +02:00
Jan Decaluwe
fb9255bfa2 Added support for constants in ConcatSignal interface 2015-05-23 01:13:39 +02:00
jandecaluwe
9c605db9f1 Merge pull request #74 from josyb/TristateSignal-VHDL-conversion 
_toVHDL: Added correct tristate assignment for std_logic signal
 2015-05-23 00:12:59 +02:00
Josy Boelen
f9651328f6 _toVHDL: Added correct tristate assignment for std_logic signal 2015-05-19 17:38:37 +02:00
jandecaluwe
890202329c Merge pull request #71 from cfelton/test_always_seq 
Test always seq
 2015-05-06 08:39:52 +02:00