FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
1,123 Commits 9 Branches 41 Tags
Commit Graph

1123 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jan Decaluwe
1a438778b9 introduced vsim as unit test simulator (both with vlog and vcom) 2010-09-11 23:08:51 +02:00
Jan Decaluwe
c39972585d hex repr for case items 2010-07-29 21:30:31 +02:00
Jan Decaluwe
060931ef49 semicolon after Verilog instantiation 2010-07-27 23:11:22 +02:00
Jan Decaluwe
25ae54a168 sized bitstrings in concat 2010-07-27 22:18:35 +02:00
Jan Decaluwe
49ed1d7432 Verilog memories are potentially wires 2010-07-27 21:12:35 +02:00
Jan Decaluwe
7c655e881c Systematic coercion to int in slicing and indexing 2010-07-25 13:22:19 +02:00
Jan Decaluwe
95de2884e7 finer control of _driven attribute for ShadowSignals 2010-07-22 11:32:55 +02:00
Jan Decaluwe
565d29f746 better handling of memories and list of signals 2010-07-22 11:12:56 +02:00
Jan Decaluwe
812757b76e removed print 2010-07-21 13:17:02 +02:00
Jan Decaluwe
4e8ccc15a3 prefer case over casez if possible 2010-07-21 13:11:28 +02:00
Jan Decaluwe
b69ace1b99 renamed suppress_myhdl_header to no_myhdl_header 2010-07-21 12:41:39 +02:00
Jan Decaluwe
aae47cb044 fixed bugs with if to case mapping 2010-07-21 12:23:07 +02:00
Jan Decaluwe
79425da593 branch merge 2010-07-20 13:21:29 +02:00
Jan Decaluwe
3690496bff fixed bug related to enum in simple always_comb 2010-07-20 13:14:37 +02:00
Knut Eldhuset
f5a5539c93 Enum types are sorted before printing, ensuring deterministic output. 
--HG--
branch : determinism
 2010-07-16 07:48:54 +02:00
Jan Decaluwe
ce14fd90af Support for custom file headers 2010-07-05 16:48:52 +02:00
Jan Decaluwe
9c2b13419b Support for string.Template with vhdl_code and verilog_code attributes 2010-07-05 15:24:17 +02:00
Jan Decaluwe
f44fcfebc3 Use signals directly for indexing with __index__ 2010-07-03 19:09:40 +02:00
Jan Decaluwe
62ace46b26 Improve hiearchical handling of ShadowSignals 2010-07-03 15:12:58 +02:00
Jan Decaluwe
1b4e8706b2 support for user-requested instances 2010-07-02 23:20:24 +02:00
Jan Decaluwe
563777f43d added vhdl_code and verilog_code function attribute as alternative to magic variables 2010-07-02 18:03:00 +02:00
Jan Decaluwe
5a2c6a89b4 refactoring 2010-07-02 16:55:02 +02:00
Jan Decaluwe
e4ff6deccf refactoring 2010-07-02 15:12:44 +02:00
Jan Decaluwe
52a5afa8cc example package 2010-07-02 13:25:24 +02:00
Jan Decaluwe
3b4e7dc293 examples 2010-07-02 13:24:04 +02:00
Jan Decaluwe
4cad5a171e Support for conversion of ternary operator. 
They are converted to ternary equivalents in the target HDL.
If possible, they are converted to single line assigns.
Within a process, this will only work with VHDL-2008.
 2010-07-01 19:13:42 +02:00
Jan Decaluwe
1f79dd17f8 prepare _extractHierarchy for further patches 2010-07-01 12:46:21 +02:00
Jan Decaluwe
7c48c2e171 addition doc writing calls 2010-06-29 16:51:46 +02:00
Jan Decaluwe
51c057fbf6 docstrings forwarded to conversion output 
Official docstrings are put on a hopefully logical place,
but unofficial docstrings are also supported. This provides
a way to control which comments go the converted output, and
which don't (i.e. ordinary Python commnents).
 2010-06-29 16:41:13 +02:00
Jan Decaluwe
5fe347ff13 better support for mapping to case statements 2010-06-22 17:46:44 +02:00
Jan Decaluwe
84ee1bd778 fix to only skip docstrings, not other expressions 2010-06-22 15:03:34 +02:00
Jan Decaluwe
02a9b35798 skip doc string for always_comb block inference 2010-06-22 14:40:13 +02:00
Jan Decaluwe
96ad4abbcd docstrings in Verilog output 2010-06-22 13:28:51 +02:00
Jan Decaluwe
1ab5fccce8 support for custom file headers in toVerilog 2010-06-22 11:26:31 +02:00
Jan Decaluwe
69b9225e67 support for optional represention of integer literals has hex numbers 2010-06-22 10:15:48 +02:00
Jan Decaluwe
c61634f759 removed parallel_case / full_case synthesis directives 2010-06-22 09:37:17 +02:00
Jan Decaluwe
9fb95914d5 optional support for blocking assignments only in combinatorial always blocks 2010-06-21 23:32:30 +02:00
Jan Decaluwe
763ae51960 support for toVerilog.standard, 1995 uses 'or' in sensitivity lists 2010-06-21 22:55:55 +02:00
Jan Decaluwe
115afff6c6 ugly hack to detect orphan else clause for template transformation 2010-06-21 10:48:35 +02:00
Jan Decaluwe
c11f7b9458 fix for if-then-else flattening 2010-06-21 09:14:48 +02:00
Jian Luo
2afac7e7e1 fixed if-elif to case conversion into Verilog 
but conversion into VHDL still fails
 2010-06-20 13:50:29 +02:00
Jan Decaluwe
9799ddb9a9 make sure SIMPLE_ALWAYS_COMB supports lists of signals 2010-06-20 16:54:24 +02:00
Jan Decaluwe
bdeb8c0805 Solved edge inference bug 2010-06-20 14:56:25 +02:00
Jan Decaluwe
34fd26e5a8 changed test to expose edge inference bug 2010-06-20 14:48:35 +02:00
Jan Decaluwe
f32b415dbe additional flag for newer linuxes or gcc's 2010-06-20 13:25:14 +02:00
Jan Decaluwe
58395fb76a error message bug 2010-06-20 13:24:28 +02:00
Jan Decaluwe
83bec53dec smarter prefix handling in hierarchy 2010-06-12 20:17:21 +02:00
Jian Luo
2066201d5d fix a VHDL conversion failure when function has a argument of type 'enum' 2010-06-11 15:38:02 +02:00
Jan Decaluwe
0d7a030e26 Introduced SignalType for instance type checking on Signal objects 2010-06-12 09:45:12 +02:00
Benoit Allard
79a1498e34 Improve Error messages 2009-12-15 18:24:52 +01:00