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Author	SHA1	Message	Date
jand	3d07a41c2c	*** empty log message ***	2005-12-09 15:16:09 +00:00
jand	f1a73b4923	partial checkin	2005-12-09 14:58:42 +00:00
jand	4c78b0821c	better error msg	2005-12-08 09:25:04 +00:00
jand	31be8b4034	naming	2005-12-06 22:14:55 +00:00
jand	64251edae7	instance	2005-12-05 16:25:46 +00:00
jand	0b53eb97ec	adapted to 0.5	2005-12-05 12:22:35 +00:00
jand	b5ddc597dc	reference 0.5	2005-12-05 11:45:46 +00:00
jand	fe7816ce29	driven but unused signal warning	2005-11-30 10:54:58 +00:00
jand	e2ffd84e97	preparing alpha rel_0-5a1	2005-11-27 15:42:58 +00:00
jand	d4fe440519	posedge/negedge functions replace by attributes	2005-11-25 15:42:40 +00:00
jand	813e23c2a1	edge attributes instead of functions	2005-11-25 10:06:11 +00:00
jand	2c72b25c9d	waiter inference on edge attributes ... instance test	2005-11-25 09:53:43 +00:00
jand	58218d7df3	always error checks	2005-11-24 17:53:20 +00:00
jand	3c78606452	inference on _always_comb waiters	2005-11-24 14:49:58 +00:00
jand	93440598e9	error reporting with user defined verilog	2005-11-22 21:00:48 +00:00
jand	307dca2f2c	Introduce base classes EnumType and EnumItemType, for type checking only	2005-11-21 17:03:08 +00:00
jand	7c39ec52a9	__verilog__ in generator functions not supported	2005-11-21 16:42:37 +00:00
jand	1c26dd31b5	driven attribute values	2005-11-21 16:37:44 +00:00
jand	f707d0024a	dev5 rel_0-5dev5	2005-11-21 11:07:14 +00:00
jand	1c3a13c946	fine-grained signed arithmetic	2005-11-19 15:37:59 +00:00
jand	26a43394c4	user-defined verilog ... bug fixes with hierarchical naming rel_0-5dev4	2005-11-13 21:09:42 +00:00
jand	28258b40ff	custom Verilog code test	2005-11-09 15:42:56 +00:00
jand	acc510f5ba	signed arithmetic rel_0-5dev3	2005-11-04 09:07:13 +00:00
jand	0dd0b8a8a9	proper intbv initialization	2005-10-22 19:19:39 +00:00
jand	df1c7303e5	delay object rel_0-5dev2	2005-10-21 15:01:41 +00:00
jand	2bb55f5e65	we	2005-10-21 09:39:29 +00:00
jand	0e564e672d	decorators	2005-10-21 09:37:50 +00:00
jand	14cc82a27b	always, instance decorator ... always_comb as decorator	2005-10-18 12:08:07 +00:00
jand	8c4408a7b6	0.5 development rel_0-5dev1	2005-10-07 08:24:44 +00:00
jand	80a35851ad	start signed support ... None default value of intbv	2005-10-06 20:08:36 +00:00
jand	2584fa6b59	at least 2.4	2005-10-06 20:08:06 +00:00
jand	f0fe17b639	added clean target	2005-10-03 16:07:46 +00:00
jand	a9969b0e15	new version of cver	2005-10-03 15:49:57 +00:00
jand	6d292f6e19	object files name suffic .o	2005-10-03 15:49:36 +00:00
jand	dd4760d43f	handle leaf generators properly	2005-09-17 19:28:41 +00:00
jand	7c3206da5a	clean up	2005-09-15 15:47:44 +00:00
jand	f28e09ee29	removed special generator handling	2005-09-15 15:45:55 +00:00
jand	29fa0d50b3	start to support signed	2005-09-14 14:19:40 +00:00
jand	395709cae0	simplified hierarchy extraction ... get rid of findInstanceName	2005-09-14 09:25:59 +00:00
jand	7f11aadc89	adapted traceSignals to use func_name	2005-09-09 09:15:25 +00:00
jand	fba110a473	toVerilog is now a callable instance	2005-09-09 09:15:07 +00:00
jand	60d6cc0142	adapted traceSignals to use func_name, like toVerilog	2005-09-09 09:13:07 +00:00
jand	1750cb0f3c	changed toVerilog to use func_name for file naming	2005-09-08 08:18:23 +00:00
jand	78a68234c3	added	2005-08-19 15:13:55 +00:00
jand	333e2042db	Support for mapping tuple of ints to case statements	2005-08-19 15:11:39 +00:00
jand	5a555f32ac	signal names have priority on list of signals	2005-08-17 17:16:01 +00:00
jand	e940e3d213	Support for lists of signals mapping to Verilog mem	2005-08-09 13:50:03 +00:00
jand	4f645619d4	simple always blocks to assign statements ... non-local objects should be signals check	2005-08-05 09:48:59 +00:00
jand	8225583303	memory support	2005-08-01 09:10:39 +00:00
jand	fa4aa9bbd6	added	2005-07-18 12:05:25 +00:00