45 Commits

Author	SHA1	Message	Date
Jan Decaluwe	4189d9ba95	Bug fix merge from default ... --HG-- branch : 0.9-dev	2013-09-15 22:36:59 +02:00
Jan Decaluwe	cb82cad878	version number	2013-09-15 22:34:40 +02:00
Jan Decaluwe	41ee7bb219	0.8 doc improvements	2013-05-16 00:38:14 +02:00
Jan Decaluwe	aa70757209	Version number 0.8 ... --HG-- branch : 0.8-dev	2013-05-13 17:16:44 +02:00
Jan Decaluwe	9eacce1ebb	added draft implementation of modbv.py and corresponding benchmark updates ... --HG-- branch : 0.8-dev	2011-05-21 13:33:25 +02:00
Jan Decaluwe	4915a896e0	Prepare _intbv for subclassing ... --HG-- branch : 0.8-dev	2011-05-21 09:19:41 +02:00
Jan Decaluwe	52814f1eb3	Version number 0.7	2010-12-19 18:20:35 +01:00
Jan Decaluwe	75d85e4b98	setup 0.7dev in default branch	2009-04-25 16:51:01 +02:00
Jan Decaluwe	7255653ed2	version number 0.6	2008-12-21 15:42:55 +01:00
Jan Decaluwe	ce3e8c00b2	Updated copyright notice, removed keyword expansion symbols	2008-12-02 11:08:08 +01:00
Jan Decaluwe	1697a4fab0	prepare for development release	2008-08-21 15:29:10 +02:00
jand	47fa6fc544	Solved bug related to bit inversion ins expressions ... when converted to VHDL	2008-03-27 16:52:40 +00:00
jand	32f75dd80b	support for min and max attribute conversion	2008-01-30 08:53:53 +00:00
jand	77a0d8c1d4	conversion bug from IPROBE project	2007-12-20 13:53:23 +00:00
jand	d30bac487d	0.6dev5 setup	2007-06-28 20:45:16 +00:00
jand	9b92962595	move to 0.6dev4 ... fix custom Verilog test	2007-01-12 21:37:43 +00:00
jand	39a2603d92	augmented assigns	2006-11-07 11:57:26 +00:00
jand	cd72fbb29f	ram	2006-10-12 20:32:06 +00:00
jand	e5d346b79d	manifest	2006-10-04 15:28:04 +00:00
jand	bc8aa99816	version number	2006-10-04 15:15:32 +00:00
jand	77e2887c47	to 0.5.1	2006-04-27 11:01:34 +00:00
jand	d96efbcb3f	before going to svn	2006-03-08 16:04:18 +00:00
jand	fb3b4393bc	0.5	2005-12-27 16:55:12 +00:00
jand	a351bf27a2	0.5c1	2005-12-27 14:48:54 +00:00
jand	e06395abe6	beta	2005-12-19 13:00:25 +00:00
jand	93440598e9	error reporting with user defined verilog	2005-11-22 21:00:48 +00:00
jand	f707d0024a	dev5	2005-11-21 11:07:14 +00:00
jand	26a43394c4	user-defined verilog ... bug fixes with hierarchical naming	2005-11-13 21:09:42 +00:00
jand	acc510f5ba	signed arithmetic	2005-11-04 09:07:13 +00:00
jand	0e564e672d	decorators	2005-10-21 09:37:50 +00:00
jand	2584fa6b59	at least 2.4	2005-10-06 20:08:06 +00:00
jand	b4b6415a34	0.4.1	2004-03-03 09:56:04 +00:00
jand	b4057b2ee7	toVerilog package	2004-02-04 17:13:07 +00:00
jand	0acccaa497	0.4	2004-01-07 21:36:05 +00:00
jand	7d68a65274	0.4	2004-01-07 21:28:04 +00:00
jand	7ce730cb30	adapted for register	2003-09-08 07:45:10 +00:00
jand	3464205194	new version	2003-09-08 07:15:41 +00:00
jand	66de4f10e9	prepare release	2003-07-31 10:21:48 +00:00
jand	f2bf4c33f3	added	2003-07-22 22:02:20 +00:00
jand	64b7252ec5	adapted MANIFEST.in for future release	2003-06-02 15:20:42 +00:00
jand	ecb8d1d0bb	license	2003-05-17 15:41:33 +00:00
jand	eec897efdc	started with 0.2	2003-04-01 19:44:13 +00:00
jand	b8d77aca7b	version check	2003-01-30 17:19:02 +00:00
jand	c2813f5d6e	Top-level test	2003-01-30 12:19:52 +00:00
jand	45b4e25be4	Put into a project	2003-01-23 23:21:31 +00:00