FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
1,021 Commits 9 Branches 41 Tags
Commit Graph

1021 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Guenter Dannoritzer
515265773a Fixed typos in the manual 2008-12-09 13:42:22 +01:00
Guenter Dannoritzer
df3b5d5c54 Added another index entry for intbv conversion 2008-12-09 12:50:31 +01:00
Guenter Dannoritzer
d3929bea20 Added index entry to intbv conversion documentation 2008-12-09 12:39:06 +01:00
Guenter Dannoritzer
e6ac4e8bef Added examples of intbv instantiation 
Added some examples about creating intbv instances in the subsection
"Bit oriented operations" of the manual.
Did some small rewording in the bit slicing subsection.
 2008-12-09 12:12:34 +01:00
Guenter Dannoritzer
75c474bfea Fixed small formating error in the signed() section 2008-12-05 15:49:50 +01:00
Jan Decaluwe
fbf38849ea Solve some VHDL conversion bugs from filter project 2008-12-04 11:25:29 +01:00
Jan Decaluwe
eaafdaa33f Added tag rel_0-6dev10 for changeset 15b58c07d987 2008-12-02 11:20:58 +01:00
Jan Decaluwe
8b8d6cf206 Removed tag rel_0-6dev10 rel_0-6dev10 2008-12-02 11:13:11 +01:00
Jan Decaluwe
0e6dfe8f48 Merge 2008-12-02 11:12:37 +01:00
Jan Decaluwe
c75b08532f Added tag rel_0-6dev10 for changeset 5e746c91ea7a 2008-12-02 11:08:22 +01:00
Jan Decaluwe
ce3e8c00b2 Updated copyright notice, removed keyword expansion symbols 2008-12-02 11:08:08 +01:00
Jan Decaluwe
141c10fcae Added missing test file 2008-12-01 23:01:53 +01:00
Jan Decaluwe
10c39e9790 Added intbv.signed conversion test based on core test. 
This test includes slices and concats. Some issues came up that
required further changes to the convertor code.
 2008-12-01 17:15:21 +01:00
Jan Decaluwe
e271afb710 intbv.signed support with print test 2008-11-30 16:30:30 +01:00
Jan Decaluwe
b9d083e10f fixed some reported typo's 2008-11-26 00:56:41 +01:00
Jan Decaluwe
e6ed18682b sidebar style adaptation 2008-11-25 17:40:13 +01:00
Jan Decaluwe
0db279f70a updated preface 2008-11-25 17:06:48 +01:00
Jan Decaluwe
03aff647eb Added documentation about handling hierarchy 2008-11-25 16:40:37 +01:00
Jan Decaluwe
dcc6d147e1 Reworked documentation about user-defined code 2008-11-24 21:26:26 +01:00
Jan Decaluwe
4cb56fbd12 improved conversion examples doc 2008-11-23 23:24:38 +01:00
Jan Decaluwe
d23f0f303d Added VHDL examples to documentation 2008-11-23 22:36:16 +01:00
Jan Decaluwe
611457033e used 0.6 version number for examples 2008-11-23 11:36:16 +01:00
Jan Decaluwe
f18a2664bf Added conversion examples from manual 2008-11-22 22:40:25 +01:00
Jan Decaluwe
4e6e3da748 Moved vhdl enum types to separate package. 
This is cleaner and now ports can also have enum types.
In the future, more things can be added to the package.
 2008-11-21 21:32:17 +01:00
Jan Decaluwe
d5ab95ff1b updated conversion examples from manual for VHDL 2008-11-19 21:19:13 +01:00
Jan Decaluwe
fa723b9840 test bench conversion, cosimulation, decorator documentation 2008-11-19 00:58:51 +01:00
Jan Decaluwe
c0138bb2f6 doc about issues with VHDL cosimulation 2008-11-18 00:13:12 +01:00
Jan Decaluwe
e215aae210 Added template transformation section 2008-11-16 09:22:48 +01:00
Jan Decaluwe
32e10d5898 Put conversion examples in separate chapter 2008-11-16 09:15:32 +01:00
Jan Decaluwe
e1cce08a23 conversion doc restructuring 2008-11-15 18:14:04 +01:00
Jan Decaluwe
f8ccaceb4a Updated type mapping and supported statements documentation 2008-11-15 16:52:25 +01:00
Jan Decaluwe
4b3bcfac8f conversion doc updates 2008-11-15 00:06:37 +01:00
Jan Decaluwe
9a1da9df62 conversion chapter 2008-11-12 23:46:53 +01:00
Jan Decaluwe
dc1b33f114 Partial update of conversion chapter 2008-11-12 19:08:11 +01:00
Jan Decaluwe
cbb30b0da5 Improved type mapping explanation 2008-11-12 16:37:53 +01:00
Jan Decaluwe
03e2e8b55f Updated manual preface 2008-11-12 00:17:21 +01:00
Jan Decaluwe
943933aa37 support for signed Verilog memories 2008-11-11 23:15:26 +01:00
Jan Decaluwe
6087af55d7 Doc updates, parts of VHDL conversion info to reference 2008-11-09 19:47:03 +01:00
Jan Decaluwe
35a182c8a8 doc proofread 2008-11-07 23:52:33 +01:00
Jan Decaluwe
8f378b2849 registration doc update 2008-11-07 21:53:08 +01:00
Jan Decaluwe
fdfead0356 Custom stylesheet 2008-11-07 16:18:33 +01:00
Jan Decaluwe
18d41d80a5 support for enum_encoding attribute 2008-11-07 14:57:56 +01:00
Jan Decaluwe
4a46629ddb conversion error messages on unsupported format strings 
(width and justifcation specifiers are not supported)
 2008-11-05 20:44:18 +01:00
Jan Decaluwe
975eba937a Added checks of list of signal limitations. 
* Top-level ports in lists are not allowed
* Signals in multiple lists are not allowed.
The reason is that these cases cannot be converted to
equivalent Verilog or VHDL.
 2008-10-21 09:53:01 +02:00
Jan Decaluwe
3c0da6a6c7 Moved print error tests to general test 2008-09-27 13:27:51 +02:00
Jan Decaluwe
ac74c06050 First complete pass on whatsnew doc 2008-09-26 15:46:16 +02:00
Jan Decaluwe
5403c6fb1e whatsnew new sections 2008-09-24 17:41:09 +02:00
Jan Decaluwe
c04a08657a whatsnew doc improvement 2008-09-23 23:55:43 +02:00
Jan Decaluwe
3a3e0e6a3e partial rewrite of whatsnew doc 2008-09-23 17:33:38 +02:00
Jan Decaluwe
5a59d04e6f Added whatsnew document 2008-09-22 20:16:11 +02:00