FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
1,541 Commits 9 Branches 41 Tags
Commit Graph

1541 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Keerthan Jaic
78eba1bb37 fix _convutils references 2015-02-25 20:52:29 -08:00
Keerthan Jaic
bbeb992115 merge util and convutils 2015-02-25 20:52:12 -08:00
Keerthan Jaic
2c14cefbcb Fix format string for py2.6 compatibility 2015-02-25 20:52:08 -08:00
Keerthan Jaic
c2021eb8c7 Remove unsupported type check in _analyze.py since it is already done in _toVerilog,_toVHDL 2015-02-25 20:51:53 -08:00
Keerthan Jaic
5d4ebcdf0c travis: disable email notificatoins 2015-02-25 20:41:56 -08:00
Keerthan Jaic
42e9645ea4 add ci script and travis.yml 2015-02-25 20:32:11 -08:00
Keerthan Jaic
e459c42dd0 Create gitignore 2015-02-25 19:56:56 -08:00
jandecaluwe
a439a92b4d Merge pull request #4 from josyb/master 
set correct length when initialising an intbv with a binary string containing underscores
 2015-02-25 21:00:49 +01:00
Josy Boelen
afd91bdc8d set correct length when initialising an intbv with a binary string containing underscores 2015-02-25 20:51:30 +01:00
jandecaluwe
912938283d Merge pull request #3 from cfelton/master 
Updated 0.9 documentation.
 2015-02-23 14:13:55 +01:00
Christopher Felton
1513a24e18 Updated 0.9 documentation. 
Updated the MyHDL manual to include the 0.9 what's new in the
index and additional verbage in the conversion section on
interfaces.  This commit is also being used as a test vehicle
for the new development flow using git.
 2015-02-22 18:52:09 -06:00
jandecaluwe
f6ece0d097 Merged in heng/myhdl/0.9-dev-set_file_dir (pull request #19) 
Adding a directory attribute to toVHDL and toVerilog

--HG--
branch : 0.9-dev
 2015-02-19 21:12:01 +01:00
Henry Gomersall
684c65ff60 Merge in branches from main repository. 
--HG--
branch : 0.9-dev-set_file_dir
 2015-02-19 12:34:54 +00:00
Henry Gomersall
b196271e8d Made sure the no_testbench state was maintained despite the test. Also added behavioural docstrings to the test code. 
--HG--
branch : 0.9-dev-set_file_dir
 2015-02-19 12:32:47 +00:00
heng
b67145c003 Merged jandecaluwe/myhdl/0.9-dev into 0.9-dev-set_file_dir 
--HG--
branch : 0.9-dev-set_file_dir
 2015-02-19 12:20:24 +00:00
Jan Decaluwe
940608135a Merge 
--HG--
branch : 0.9-dev
 2015-02-18 22:05:28 +01:00
Henry Gomersall
f83dbe835d Added tests, code and docs to implement directory setting for toVHDL and toVerilog. 
--HG--
branch : 0.9-dev-set_file_dir
 2015-02-18 20:38:49 +00:00
Jan Decaluwe
3d0114ea83 Merge from default 
--HG--
branch : 0.9-dev
 2015-02-18 19:01:04 +01:00
jandecaluwe
d2ba09a6f2 Merged in alexforencich/myhdl/vpi_fix (pull request #16) 
Allow more arguments in icarus verilog VPI
 2015-02-18 18:55:58 +01:00
Josy Boelen
f521550b35 see issue #29: ListOfSIgnals in VHDL sensitivity list 
--HG--
branch : 0.9-dev
 2015-02-18 10:04:03 +01:00
Alex Forencich
5df9e4b89b new branch vpi_fix 
--HG--
branch : vpi_fix
 2015-02-17 21:39:57 -08:00
jandecaluwe
1492b56ce5 Merged in josyb/myhdl/0.9-dev (pull request #15) 
Helper function returning *enum* type, modbv __repr__()

--HG--
branch : 0.9-dev
 2015-02-16 18:43:25 +01:00
Jan Decaluwe
cc05bbb3f0 No idea how this got closed 
--HG--
branch : 0.9-dev
 2015-02-16 18:42:18 +01:00
jandecaluwe
68f51d198e Close branch 0.9-dev 
--HG--
branch : 0.9-dev
 2015-02-16 18:27:03 +01:00
jandecaluwe
be0a31b21d Merged in heng/myhdl/0.9-dev-doctest (pull request #14) 
Doctests for rtl.rst

--HG--
branch : 0.9-dev
 2015-02-16 17:42:25 +01:00
Josy Boelen
b9fcfe69db added toStr() for enum type 
--HG--
branch : 0.9-dev
 2015-02-16 13:50:09 +01:00
Josy Boelen
f3bac23a7c see: http://article.gmane.org/gmane.comp.python.myhdl/3540 
--HG--
branch : 0.9-dev
 2015-02-16 13:24:27 +01:00
Henry Gomersall
1ee356c6b4 Merging in mainline. 
--HG--
branch : 0.9-dev-doctest
 2015-02-11 15:56:38 +00:00
Christopher Felton
5c2d8452c9 updated 0.9 what's new 
--HG--
branch : 0.9-dev
 2015-02-08 20:08:53 -06:00
Henry Gomersall
1511dd6de0 Simplified the mux doctest to only have one copy of the code. 
--HG--
branch : 0.9-dev
 2015-01-09 11:14:35 +00:00
Henry Gomersall
7a5b6fc0ff Merged with mainline. 
--HG--
branch : 0.9-dev
 2015-01-04 17:27:08 +00:00
Henry Gomersall
346cafa374 Added the FSM in rtl.rst to the doctest code. 
--HG--
branch : 0.9-dev
 2015-01-04 17:21:09 +00:00
Henry Gomersall
b540d4608c Set the correct initialisation value for the FSM example in docs. 
--HG--
branch : 0.9-dev
 2015-01-04 16:40:04 +00:00
Henry Gomersall
0230cdccfa corrected False to be a synchronous reset in the reference docs 
--HG--
branch : 0.9-dev
 2015-01-04 16:35:29 +00:00
Henry Gomersall
72c8ebdf97 Fixed up the doctest code in rtl.rst to pass the tests. 
--HG--
branch : 0.9-dev
 2015-01-04 16:28:47 +00:00
Henry Gomersall
df2dfb0480 Merging in Chris Feltons initial doctest work 
--HG--
branch : 0.9-dev
 2015-01-04 14:53:39 +00:00
Alex Forencich
292cb2e086 Allow more arguments in icarus verilog VPI 2014-11-18 12:30:39 -08:00
Jan Decaluwe
050d3f1917 Fix download url 2014-08-26 10:59:59 +02:00
Jan Decaluwe
34948430c9 Added tag 0.8.1 for changeset 0f5597633e99 2014-08-26 10:19:06 +02:00
Jan Decaluwe
1903677a56 status 0.8.1 2014-08-26 10:06:55 +02:00
Jan Decaluwe
eecafe20ac Merge default 
--HG--
branch : 0.9-dev
 2014-08-25 20:28:48 +02:00
Jan Decaluwe
ca04541cd0 Prepare for 0.8.1 release 2014-08-25 20:27:31 +02:00
Jan Decaluwe
94c827a8fe Merge from default 
--HG--
branch : 0.9-dev
 2014-08-24 16:36:22 +02:00
Jan Decaluwe
a62a14cf01 Fixed issue #13 2014-08-24 16:35:52 +02:00
Jan Decaluwe
d6212cdd4f Merge from default 
--HG--
branch : 0.9-dev
 2014-08-24 10:39:07 +02:00
Jan Decaluwe
77f6c638a3 added test case with fully specified intbv checks 2014-08-24 10:37:56 +02:00
Jan Decaluwe
3783aebbbb Fix links 2014-08-24 08:44:33 +02:00
Jan Decaluwe
6481ff6caa Merge from default 
--HG--
branch : 0.9-dev
 2014-08-12 16:17:41 +02:00
Jan Decaluwe
95ba19e558 Test name fix 2014-08-12 16:16:58 +02:00
Jan Decaluwe
77de13ac66 Fixed issue #10 (2) 2014-08-12 16:15:21 +02:00