Jan Decaluwe
611457033e
used 0.6 version number for examples
2008-11-23 11:36:16 +01:00
Jan Decaluwe
f18a2664bf
Added conversion examples from manual
2008-11-22 22:40:25 +01:00
Jan Decaluwe
4e6e3da748
Moved vhdl enum types to separate package.
...
This is cleaner and now ports can also have enum types.
In the future, more things can be added to the package.
2008-11-21 21:32:17 +01:00
Jan Decaluwe
d5ab95ff1b
updated conversion examples from manual for VHDL
2008-11-19 21:19:13 +01:00
Jan Decaluwe
fa723b9840
test bench conversion, cosimulation, decorator documentation
2008-11-19 00:58:51 +01:00
Jan Decaluwe
c0138bb2f6
doc about issues with VHDL cosimulation
2008-11-18 00:13:12 +01:00
Jan Decaluwe
e215aae210
Added template transformation section
2008-11-16 09:22:48 +01:00
Jan Decaluwe
32e10d5898
Put conversion examples in separate chapter
2008-11-16 09:15:32 +01:00
Jan Decaluwe
e1cce08a23
conversion doc restructuring
2008-11-15 18:14:04 +01:00
Jan Decaluwe
f8ccaceb4a
Updated type mapping and supported statements documentation
2008-11-15 16:52:25 +01:00
Jan Decaluwe
4b3bcfac8f
conversion doc updates
2008-11-15 00:06:37 +01:00
Jan Decaluwe
9a1da9df62
conversion chapter
2008-11-12 23:46:53 +01:00
Jan Decaluwe
dc1b33f114
Partial update of conversion chapter
2008-11-12 19:08:11 +01:00
Jan Decaluwe
cbb30b0da5
Improved type mapping explanation
2008-11-12 16:37:53 +01:00
Jan Decaluwe
03e2e8b55f
Updated manual preface
2008-11-12 00:17:21 +01:00
Jan Decaluwe
943933aa37
support for signed Verilog memories
2008-11-11 23:15:26 +01:00
Jan Decaluwe
6087af55d7
Doc updates, parts of VHDL conversion info to reference
2008-11-09 19:47:03 +01:00
Jan Decaluwe
35a182c8a8
doc proofread
2008-11-07 23:52:33 +01:00
Jan Decaluwe
8f378b2849
registration doc update
2008-11-07 21:53:08 +01:00
Jan Decaluwe
fdfead0356
Custom stylesheet
2008-11-07 16:18:33 +01:00
Jan Decaluwe
18d41d80a5
support for enum_encoding attribute
2008-11-07 14:57:56 +01:00
Jan Decaluwe
4a46629ddb
conversion error messages on unsupported format strings
...
(width and justifcation specifiers are not supported)
2008-11-05 20:44:18 +01:00
Jan Decaluwe
975eba937a
Added checks of list of signal limitations.
...
* Top-level ports in lists are not allowed
* Signals in multiple lists are not allowed.
The reason is that these cases cannot be converted to
equivalent Verilog or VHDL.
2008-10-21 09:53:01 +02:00
Jan Decaluwe
3c0da6a6c7
Moved print error tests to general test
2008-09-27 13:27:51 +02:00
Jan Decaluwe
ac74c06050
First complete pass on whatsnew doc
2008-09-26 15:46:16 +02:00
Jan Decaluwe
5403c6fb1e
whatsnew new sections
2008-09-24 17:41:09 +02:00
Jan Decaluwe
c04a08657a
whatsnew doc improvement
2008-09-23 23:55:43 +02:00
Jan Decaluwe
3a3e0e6a3e
partial rewrite of whatsnew doc
2008-09-23 17:33:38 +02:00
Jan Decaluwe
5a59d04e6f
Added whatsnew document
2008-09-22 20:16:11 +02:00
Jan Decaluwe
85f2db5233
Improved new documentation setup
2008-09-21 09:55:14 +02:00
Jan Decaluwe
2b91828d37
Verilog print support for enum types
2008-09-20 15:44:34 +02:00
Jan Decaluwe
5f3b1aa469
Make enum type implementation more explicit
2008-09-19 20:38:07 +02:00
Jan Decaluwe
43f69f1e80
Proper support for converting multiple print arguments
2008-09-16 21:30:42 +02:00
Jan Decaluwe
a2ba8f2a30
Code for signal tracing and conversion now assumes decorator usage.
...
From now on, all such code should always use decorators for blocks
that are part of the structure of the design. This makes the
purpose of the code clearer and allows simplifications and useful
assumptions for the MyHDL implementation.
Conversion support for other kind of generators has been removed.
The 'instances' function now only returns blocks that are
constructed using decorators at their leaf cells.
2008-09-15 16:47:15 +02:00
Jan Decaluwe
27ad2f5fa8
Some code clean up, moved _isGenSeq function
2008-09-14 09:10:36 +02:00
Jan Decaluwe
1accf14232
Refactored always block header and sensitivity list writing
2008-09-12 14:43:59 +02:00
Jan Decaluwe
4a8436745c
Support for list of signals in sensitivity lists of general @instance blocks
2008-09-10 23:04:33 +02:00
Jan Decaluwe
ebb99727b6
Added list of signal test for general @instance block
2008-09-10 20:11:15 +02:00
Jan Decaluwe
65b3295cb4
Support for list of signals in the sensitivity list of simple @instance blocks.
2008-09-10 17:26:59 +02:00
Jan Decaluwe
8e8550c801
Add lists of signals to the inferred sensitivity list in an always_comb
2008-09-09 20:47:11 +02:00
Jan Decaluwe
7a2b3f2089
Support wire memories, to use in assign statemtent.
...
Seems like cver doesn't support this, but Icarus does. Apparently
a Verilog 2001 feature.
2008-09-09 16:08:21 +02:00
Jan Decaluwe
0959d892ea
Removed decl attribute from memories
2008-09-08 17:26:53 +02:00
Jan Decaluwe
df3eb0256c
Relax conversion constraints on list of signals.
...
Previously you couldn't use list syntax in a generator if plain
signal syntax was used for the corresponding signal in another
generator. Now list syntax gets priority if used in some generator.
In the converted output, list (memory) syntax will be used for
such signals.
Everything that worked before should continue to work unchanged.
However, cryptic "List contains Signals that are not unique to it"
should be gone.
This should make it much easier and intuitive to use lists of
signals.
2008-09-08 17:17:23 +02:00
Jan Decaluwe
8b935b24e0
Mark signals in always decorator aruments list as read
2008-09-06 16:39:01 +02:00
Jan Decaluwe
2398c4aeb9
Added test with list of sigs in sensitivity list.
...
This also required a correction of list bracket syntax in VHDL.
2008-09-06 10:54:30 +02:00
Jan Decaluwe
020c087656
use comma as sensitivity list separator systematically
2008-09-05 16:46:54 +02:00
Jan Decaluwe
ba9fd74408
cleaned up attribute lookup
2008-09-02 16:12:10 +02:00
Jan Decaluwe
61275066f9
Added method delegation to Signal, to support signed()
2008-09-02 11:23:27 +02:00
Jan Decaluwe
b81bbfb334
Merged work on decorators and some code moves
2008-09-01 20:22:41 +02:00
Jan Decaluwe
67cd0a7c90
Moved list of signals test to Signal module
2008-08-28 22:21:30 +02:00
