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Author SHA1 Message Date
forumulator
68302ecc6a Merge branch 'master' of https://github.com/jandecaluwe/myhdl 2016-03-03 17:15:49 +05:30
forumulator
89015a6fde Increased modbv test coverage 2016-03-03 17:07:05 +05:30
forumulator
5854b7d906 Increased test coverage for modbv class 2016-03-03 17:01:23 +05:30
jandecaluwe
36bb450658 Merge pull request #152 from srivatsansoft/test 
updated doc for the new public method sim.quit()
 2016-03-03 08:32:59 +01:00
srivatsansoft
8e69e0f334 updated doc for the new public method sim.quit() 2016-03-03 07:46:19 +05:30
Jan Decaluwe
28533d2541 Move to use VHDL 2008's to_string 2016-03-02 16:44:19 +01:00
Jan Decaluwe
c6613238b9 Must be dead code, no impact on test suite 2016-03-02 12:03:47 +01:00
jandecaluwe
9711dde5d6 Merge pull request #149 from srivatsansoft/master 
A single simulation instance fix for issue #104
 2016-03-01 20:57:59 +01:00
jandecaluwe
8c4ae9d186 Merge pull request #145 from punkkeks/master 
Add 'filename' attribute to traceSignals
 2016-03-01 20:39:12 +01:00
Jan Decaluwe
bb2882a6d0 Actually select the binary distro for Ubuntu 12.04 2016-03-01 19:43:15 +01:00
Jan Decaluwe
b81450ead2 typo 2016-03-01 18:02:21 +01:00
Jan Decaluwe
8aa54b797f script execution mode 2016-03-01 17:59:28 +01:00
Jan Decaluwe
e1e9ada5e8 Try ghdl 0.33 in travis 2016-03-01 17:25:23 +01:00
Jan Decaluwe
62aa73f2c2 Moved to 2008 version of ghdl - requires 0.33, expect travis fail 2016-03-01 16:06:29 +01:00
srivatsansoft
41081e3817 supporting python 2.6 2016-02-24 21:52:38 +05:30
srivatsansoft
8f0678bdea added 'from __future__ import print_function' 2016-02-24 21:31:48 +05:30
srivatsansoft
3f245896fc replaced pytest.raises with raises_kind for consistency 2016-02-24 20:32:48 +05:30
srivatsansoft
584e576b44 bug fix in _no_of_instance reset and test code updated 2016-02-24 01:01:37 +05:30
srivatsansoft
48692d4c4a changed to instance counter instead of run counter 2016-02-24 00:12:13 +05:30
srivatsansoft
0ea0fef555 A single simulation instance issue#104 2016-02-23 22:41:48 +05:30
Jan Decaluwe
755d2b8c13 Fix bitonic example; skip locals in AttrRefResolver 2016-02-03 17:24:23 +01:00
Jan Decaluwe
a48eb2e4ca Factor visitor traversal out to top class 2016-01-31 12:15:18 +01:00
Jan Decaluwe
f5de3b3af4 Reuse ast property 2016-01-31 11:52:04 +01:00
Jan Decaluwe
eb821e48c5 Correct error message 2016-01-31 10:44:42 +01:00
Jan Decaluwe
4509e56323 Cleaner interface 2016-01-31 10:31:10 +01:00
Jan Decaluwe
510c532782 Removed unused code and attributes 2016-01-31 10:09:06 +01:00
Marcel Hellwig
04b9935626 fixed mistake where I replaced filename with name 2016-01-31 01:10:05 +01:00
Marcel Hellwig
cff6f1e54e replaced self.name with name in _traceSignals 2016-01-30 21:44:46 +01:00
Marcel Hellwig
02c4f92ff6 fixed missing colon in _traceSignals 2016-01-30 21:26:46 +01:00
Jan Decaluwe
b1121a025d Refactor 2016-01-30 20:30:11 +01:00
Marcel Hellwig
ea6cba2f40 Add 'filename' attribute to traceSignals 2016-01-30 20:17:01 +01:00
Jan Decaluwe
710821d5d6 Refactor 2016-01-30 16:39:57 +01:00
Jan Decaluwe
333928b810 removed unused imports 2016-01-30 12:21:20 +01:00
Jan Decaluwe
6f3808fc68 Take this out. No idea what it was supposed to do. 2016-01-30 09:23:03 +01:00
Jan Decaluwe
82f43f056d Remove unused variable 2016-01-30 08:00:39 +01:00
Jan Decaluwe
1971a56a5c sensible default 2016-01-28 12:47:22 +01:00
Jan Decaluwe
75d53cdadb Removed unused code 2016-01-28 12:32:44 +01:00
jandecaluwe
1f960db066 Merge pull request #144 from nicmcd/master 
Add 'directory' attribute to traceSignals.
 2016-01-26 16:38:20 +01:00
Nic McDonald
94bc28f076 Add 'directory' attribute to traceSignals. 
This change does exactly what the 'directory' attribute for toVerilog and toVHDL
do. It allows the user to specify the output directory for VCD files.

This commit includes the source change, documentation change, and a py.test
change to test the functionality.
 2016-01-24 22:17:37 -08:00
jandecaluwe
fb70bb2fc4 Merge pull request #137 from nturley/master 
fix bug in test_custom tests
 2015-11-29 11:51:19 +01:00
jandecaluwe
480d228236 Merge pull request #135 from nturley/patch-1 
add test for issue 134
 2015-11-29 11:47:59 +01:00
nturley
bb2ba3c954 fix bug in test_custom tests 2015-11-15 23:50:34 -06:00
nturley
d60568ae65 fix additional issues with test_issue134 
we only need to analyze. Verify will still fail even with the fix
 2015-11-07 22:21:50 -06:00
nturley
8cc5f23dcb fix test 134 
wrong number and add xfail
 2015-11-07 21:53:35 -06:00
nturley
ed9d2a9e90 add test for issue 134 
checks for port name collision when a function names two signals with the same name
 2015-11-07 21:08:38 -06:00
Jan Decaluwe
9dffa04130 Merge branch '0.9-maintenance' 2015-11-01 21:02:07 +01:00
jandecaluwe
b726eb8139 Merge pull request #133 from clade/0.9-maintenance 
assign statement (constwires) support litterals larger than 32 bits
 2015-11-01 20:59:29 +01:00
Jan Decaluwe
65e6355e11 Added parenthesis to print 2015-11-01 20:32:19 +01:00
Jan Decaluwe
97c8c8ac7d Improve on large constant wires in VHDL 
Triggered by an reported issue with Verilog that
I was not able to reproduce (issue 133).
 2015-10-30 20:38:33 +01:00
Pierre Cladé
ff5b0b1963 assign statement (constwires) support litterals larger than 32 bits 2015-10-29 19:03:14 +01:00