jandecaluwe
983a169b16
Merge pull request #112 from josyb/TristateWarnings
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Added Code to remove inappropriate warnings on Tristate Ports and TristateDrivers
2015-07-20 08:42:00 +02:00
Josy Boelen
bdef4c0d4e
Replaced 'checking of presence of attributes' by 'isinstance' checks
2015-07-19 22:50:36 +02:00
jandecaluwe
7a104698f4
Merge pull request #111 from jck/simulators
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Various HDL simulator, conversion test improvements
2015-07-19 21:36:27 +02:00
Josy Boelen
efce467d1f
Removed warnings on Tristate ports being read, and TristateDrivers being driven but not read
2015-07-19 21:09:53 +02:00
Keerthan Jaic
ffaa33acf9
pytest: provide more useful simulator info
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* reuse registered simulators from _verify
* warn if simulator isn't found in PATH
2015-07-18 19:29:27 -04:00
Keerthan Jaic
41ce35f3dc
simplify _verify
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Rather than using many global dictionaries, just use a namedtuple
for each simulator.
2015-07-18 19:29:19 -04:00
Keerthan Jaic
dedc1ae3e0
rename icarus to iverilog, GHDL to ghdl
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This matches the name of the corresponding simulator's binary.
py.test can use this to verify is a simulator is installed before
running conversion tests
2015-07-18 13:48:16 -04:00
Keerthan Jaic
c1e0c8edad
Use pytest cli option to choose simulator in general conv tests
2015-07-18 13:48:16 -04:00
Keerthan Jaic
1ae78baadf
test_interfaces4: remove unused imports
2015-07-18 13:48:16 -04:00
Keerthan Jaic
a61daab43f
add support for nvc for VHDL verification
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https://github.com/nickg/nvc
2015-07-18 13:48:16 -04:00
Keerthan Jaic
9725ec59ca
move set_inheritable to _compat
2015-07-18 13:48:16 -04:00
Keerthan Jaic
5514c254bc
clean up modelsim cosim makefile
2015-07-18 13:48:03 -04:00
Keerthan Jaic
1a8ff95a78
Support verification for modelsim 10.4
2015-07-18 12:54:29 -04:00
Jan Decaluwe
7c531fc097
Get rid of aggregates and their issues #107
2015-07-18 15:31:58 +02:00
Jan Decaluwe
9ce3a25fa2
Improve term_op signature #107
2015-07-18 15:23:48 +02:00
Jan Decaluwe
cf3f1af80c
Fix tab issue
2015-07-18 10:51:13 +02:00
Jan Decaluwe
9bc72cc9dc
Support ternary operator without VHDL 2008 #107
2015-07-18 10:33:17 +02:00
Jan Decaluwe
9820fca461
Version 1.0dev
2015-07-18 09:59:05 +02:00
Jan Decaluwe
c038d1275c
Make toVerilog & toVHDL name attribute work with verify
2015-07-18 09:50:57 +02:00
Jan Decaluwe
88021ca2ee
Merge branch '0.9-maintenance'
2015-07-18 09:18:04 +02:00
Jan Decaluwe
4e4d3a06fd
Fix test to do what it was supposed to do
2015-07-18 09:13:44 +02:00
jandecaluwe
80b1864200
Merge pull request #103 from gitter-badger/gitter-badge
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Add a Gitter chat badge to README.md
2015-07-14 18:12:32 +02:00
The Gitter Badger
143ab48c19
Added Gitter badge
2015-07-14 16:07:19 +00:00
jandecaluwe
5360783bf8
Merge pull request #89 from iscgar/cosim_windows_support
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Windows support for co-simulation
2015-07-14 16:15:25 +02:00
jandecaluwe
494014c687
Merge pull request #93 from cfelton/test_interfaces4
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fixed VHDL variable conversion issue in test_interface4
2015-07-12 19:58:25 +02:00
Jan Decaluwe
14dc28f798
Attempt to address #98 and related issues
2015-07-12 18:21:36 +02:00
jandecaluwe
ebb7bcbc21
Merge pull request #97 from cfelton/vhdl_delay
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VHDL delay (wait) conversion fix
2015-07-11 08:24:50 +02:00
Chris Felton
67bc0b46b1
use integer instead of real for delay
2015-07-10 06:46:11 -05:00
Christopher Felton
cb01c8c710
VHDL delay (wait) conversion fix
2015-07-09 10:26:35 -05:00
Jan Decaluwe
7e3b071aa2
what's new updates
2015-07-09 09:22:33 +02:00
Jan Decaluwe
44635e7132
Streamlined interface documentation
2015-07-08 09:30:44 +02:00
Jan Decaluwe
2d6be545a7
Doc for std_logic_ports
2015-07-08 08:44:45 +02:00
Jan Decaluwe
0ede42417f
Doc update for ConcatSignal
2015-07-07 10:06:31 +02:00
jandecaluwe
01146bf25f
More consistency in doc versions
2015-07-07 08:53:12 +02:00
Jan Decaluwe
1d7b20098a
add whatsnew0.5 for completeness
2015-07-07 08:38:09 +02:00
Jan Decaluwe
e07ac7f5a0
Add old whatsnew docs to index
2015-07-06 08:52:25 +02:00
Jan Decaluwe
e1c1de7420
Version bump for 0.9.0
2015-07-06 08:26:48 +02:00
Christopher Felton
f27b351c78
fixed VHDL variable conversion issue in test_interface4
2015-07-01 19:20:43 -05:00
Isaac Garzon
841c1547ac
Added a reference comment for the set_inheritable implementation
2015-06-29 00:27:40 +03:00
jandecaluwe
a9160da3a3
Merge pull request #92 from jck/0.9-release
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0.9 docs update
2015-06-28 21:32:51 +02:00
jandecaluwe
db36c4f111
Merge pull request #91 from jck/issue_82
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fix issue 82
2015-06-28 21:31:28 +02:00
jandecaluwe
c0911ab13c
Merge pull request #90 from jck/pytest-core
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Core test improvements
2015-06-28 21:29:01 +02:00
Isaac Garzon
d3b17a56f2
Refactored set_inheritance code into the _util module
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Fixed the VPI tests for Windows
2015-06-28 20:36:09 +03:00
Keerthan Jaic
91a8148953
docs: Move old whatsnew to separate section
2015-06-27 08:47:55 -04:00
Keerthan Jaic
3b78a68981
docs: use version from myhdl.__version__
2015-06-27 08:43:37 -04:00
Keerthan Jaic
ebb1b12ff8
whatsnew update
2015-06-27 08:36:23 -04:00
Keerthan Jaic
0253256938
Fix newlines in whatsnew/0.4.rst
2015-06-27 08:14:05 -04:00
Keerthan Jaic
c8ed68d148
workaround unrelated bug in test_interfaces4
2015-06-27 07:43:12 -04:00
Keerthan Jaic
87fd17be79
test/core: some whitespace lint fixes
2015-06-27 05:27:53 -04:00
Keerthan Jaic
ce89c6a1b6
test/core: cleanup unused imports
2015-06-27 05:17:07 -04:00
