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907 Commits

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Author SHA1 Message Date
jand
773571b2d2 different script name 2008-03-27 16:46:23 +00:00
jand
b36a581e9a added image file (doesn't work with sphinx yet) 2008-03-25 16:01:28 +00:00
jand
d248c2c0b1 rearranged doc layout 2008-03-24 15:45:12 +00:00
jand
8678647c72 added new doc based on sphinx 2008-03-20 20:34:04 +00:00
jand
0464469a03 moved 2008-03-20 20:31:56 +00:00
jand
3203e3ece1 VHDL 2008-03-18 21:13:18 +00:00
jand
0785d56957 corrected path for vpi modules 2008-03-13 16:23:54 +00:00
jand
345fbc636c restructured test dirs 2008-03-13 10:07:21 +00:00
jand
3bb5e57912 rename 2008-03-13 09:56:21 +00:00
jand
d3b5aeba27 Added HDL specific for-loop requirements 
* positive step for Verilog
* unspecified step for VHDL
 2008-03-12 17:15:55 +00:00
jand
9020463980 added tests for general for-loop requirements 
factored those tests out and put in analyzer
 2008-03-12 16:50:43 +00:00
jand
7c4189fd42 Modified bit inversion operation according to newsgroup discussion. 
Added support for bit inversion on signed vars in Verilog
and VHDL conversion
 2008-03-09 14:22:25 +00:00
jand
b1e3b1a1f7 version update 2008-01-30 21:31:38 +00:00
jand
4ead4eeb3d detect variable names that shadow Signal names 2008-01-30 12:56:36 +00:00
jand
a642a95cd7 skip wrongly-placed docstrings 
(was fixed automatically with previous committed fix)
 2008-01-30 09:41:31 +00:00
jand
7e1e3322ed Discard superfluous semicolons in conversion 2008-01-30 09:24:38 +00:00
jand
32f75dd80b support for min and max attribute conversion 2008-01-30 08:53:53 +00:00
jand
12e78c5426 convert constant as argument to int call to int rel_0-6dev6 2008-01-09 16:29:51 +00:00
jand
c87f6f65f3 reset toVerilog attributes after use 2008-01-08 10:05:54 +00:00
jand
e6b9c54c3d improve assert conversion to Verilog 
make sure x-values trigger assertions
 2008-01-07 20:37:24 +00:00
jand
a45c9d4c82 timescale support 2008-01-05 19:37:44 +00:00
jand
c62987ac96 assert conversion to Verilog 
restore _intbv interator as it was before
 2008-01-05 11:40:55 +00:00
jand
c33c631a4b reverse iterator for intbv so indices match with other sequences 
write binary values for intbv's with length > 30
 2008-01-04 21:10:02 +00:00
jand
71f87b37d7 support for Signal read attribute 
convert now() function to VHDL
convert assert statements to VHDL
 2008-01-04 10:22:10 +00:00
jand
a8ee894ddf makefile 2007-12-29 12:55:32 +00:00
jand
77a0d8c1d4 conversion bug from IPROBE project 2007-12-20 13:53:23 +00:00
jand
454b2294df inout ports rel_0-6dev5 2007-12-12 15:16:29 +00:00
jand
05192b114d copy initial signal value to avoid issues with mutable types 
introduce unit name in simulator setup templates to solve
case problems with ghdl
 2007-12-05 21:41:30 +00:00
jand
c648715afe support for component declarations 2007-12-02 20:03:32 +00:00
jand
4e89b9458b Add support to remember initial value and 
restore it after a simulation has ended.
This is part of clean-up between simulations
without leaving the interpreter.
 2007-12-02 16:45:48 +00:00
jand
23bf703bfb finally add bound check to bit setting 2007-11-28 20:16:16 +00:00
jand
c8a6cbc65b signal clean-up 2007-11-23 13:35:01 +00:00
jand
35f7e672c6 delay should work with longs 2007-11-23 12:06:45 +00:00
jand
cec118c858 port usage warnings 2007-11-13 20:44:35 +00:00
jand
904e79d824 __vhdl__ 2007-09-04 09:37:05 +00:00
jand
8e6fe737c8 update 2007-07-24 21:01:27 +00:00
jand
ce195a6f51 update 2007-07-23 20:12:56 +00:00
jand
c0ce0463da update 2007-07-23 20:02:14 +00:00
jand
d30bac487d 0.6dev5 setup 2007-06-28 20:45:16 +00:00
jand
90dab3f2dd print 2007-06-28 20:44:37 +00:00
jand
6ce526f179 conversion dir 2007-06-28 20:39:57 +00:00
jand
c8e4a9a86b conversion dir set up 2007-06-28 20:37:15 +00:00
jand
b632bc0bd1 first tests 2007-06-28 20:36:39 +00:00
jand
1ae2c2e9f5 verilog test 2007-06-28 20:34:19 +00:00
jand
8ac1ab0cff sim files 2007-06-25 18:36:30 +00:00
jand
64e602e043 cver, icarus 2007-06-17 19:33:22 +00:00
jand
393fbc0414 packaged myhdl support functions 2007-06-16 14:44:01 +00:00
jand
39a9f76e72 extended print support 2007-06-12 19:07:32 +00:00
jand
f56d526ae0 tristate rename 2007-05-31 18:16:58 +00:00
jand
aff756218a tristate 2007-05-08 14:15:29 +00:00