Keerthan Jaic
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ae699ba680
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clean up types for python3
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2015-03-11 08:15:20 -04:00 |
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Keerthan Jaic
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976bef6bdf
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remove duplicated _makeAST func in analyze
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2015-03-11 08:11:01 -04:00 |
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Keerthan Jaic
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4aba3ba407
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from __future__ import absolute_import in all files for uniformity
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2015-03-11 08:08:55 -04:00 |
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Keerthan Jaic
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a0d9a4fd13
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fix relative imports for python3
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2015-03-11 08:08:29 -04:00 |
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Keerthan Jaic
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7d7a0f9255
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fix raise statements for python3
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2015-03-11 08:08:04 -04:00 |
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Keerthan Jaic
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49e7f4887e
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fix except statements for python3
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2015-03-11 08:08:01 -04:00 |
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Keerthan Jaic
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d373c4e278
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Fix print statements in setup.py
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2015-03-11 08:07:50 -04:00 |
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Keerthan Jaic
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2af83aadba
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add python 3.4 to travis
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2015-03-11 08:07:34 -04:00 |
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jandecaluwe
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6a735cbed5
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Merge pull request #26 from jck/travis
simplify ci.sh
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2015-03-11 09:05:47 +01:00 |
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Keerthan Jaic
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a8cd14a227
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simplify ci.sh
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2015-03-11 02:06:00 -04:00 |
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Jan Decaluwe
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51766a3c89
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Merge branch 'jck-travis'
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2015-03-10 22:45:17 +01:00 |
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Jan Decaluwe
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f4a6eba227
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Merge branch 'travis' of https://github.com/jck/myhdl into jck-travis
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2015-03-10 22:42:49 +01:00 |
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Jan Decaluwe
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6c2c696af0
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Fixed indentation
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2015-03-10 22:40:27 +01:00 |
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Josy Boelen
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f9ace5d4b7
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toVHDL(): added fix when assigning intbv()[1:] to std_logic
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2015-03-10 22:33:21 +01:00 |
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jmgc
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0c807810c6
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Corrected the test_ShadowSignal
Corrected a minor error that did not take into account that VHDL is not
case sensitive.
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2015-03-08 12:33:18 -04:00 |
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Keerthan Jaic
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9b3795651d
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add GHDL tests to travis
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2015-03-03 18:21:57 -05:00 |
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Shen Chen
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426dfd8246
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pretty print messages during test. exit with nonzero retcode if any test fails.
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2015-03-03 18:00:43 -05:00 |
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Jan Decaluwe
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094c0e1db7
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Fixes so that all tests run
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2015-03-03 22:36:10 +01:00 |
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Jan Decaluwe
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10040b6941
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Cleaned up tests
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2015-03-03 21:39:14 +01:00 |
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jandecaluwe
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b0acbd2897
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Merge pull request #17 from cfelton/master
added py.test test/core2 to travis
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2015-03-03 19:40:12 +01:00 |
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jandecaluwe
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0d93c22eef
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Update README.md
Fix badges
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2015-03-03 16:22:37 +01:00 |
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Jan Decaluwe
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4ddd0d0c93
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Merge branch '0.8-maintenance'
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2015-03-02 18:28:03 +01:00 |
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Jan Decaluwe
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524a2ae95a
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Solved github issue #12
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2015-03-02 18:27:02 +01:00 |
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Jan Decaluwe
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48490359d0
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Added gitignore here also
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2015-03-02 18:12:37 +01:00 |
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Chris Felton
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12d127c1db
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added py.test test/core2 to travis
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2015-03-01 18:43:57 -06:00 |
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jandecaluwe
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88487b8f7a
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Merge pull request #16 from javValverde/master
Change format of README to markdown.
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2015-02-28 20:18:12 +01:00 |
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javValverde
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e70640328b
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Merge branch 'readme'
Conflicts:
README.md
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2015-02-28 19:32:01 +01:00 |
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javValverde
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9079c4fe63
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Reference @jandecaluwe's travis account
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2015-02-28 19:28:49 +01:00 |
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javValverde
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1cf1adb3e5
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Add landscape badge to README.md
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2015-02-28 19:08:36 +01:00 |
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javValverde
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6f64189f56
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Add 1st version of landscape settings
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2015-02-28 19:07:46 +01:00 |
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javValverde
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031f88094e
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Change format of README to markdown.
Add badges for docs and build (continuous integration)
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2015-02-28 18:53:53 +01:00 |
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jandecaluwe
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69c89fa70e
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Merge pull request #11 from jck/master
conv: allow modifying bits of signals inside lists
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2015-02-27 08:44:51 +01:00 |
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Keerthan Jaic
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da340434e0
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conv: allow modifying bits of signals inside lists
This commit fixes conversion breaking while modifying bits of signal
inside list.
example: somelist[i].next[j] = something
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2015-02-26 18:19:09 -08:00 |
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jandecaluwe
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cf6f153ced
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Merge pull request #8 from cogenda/cosim_cmdline
Cosim cmdline
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2015-02-26 23:32:22 +01:00 |
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jandecaluwe
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9de8556f3e
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Merge pull request #9 from hgomersall/master
toVHDL.directory should also set where the package file is placed
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2015-02-26 22:51:01 +01:00 |
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jandecaluwe
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0eed8f4d61
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Merge pull request #7 from jck/master
Travis CI, gitignore, misc fixes
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2015-02-26 22:45:26 +01:00 |
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Keerthan Jaic
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e1400e4777
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travis: move iverilog installation to travis.yml
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2015-02-26 12:04:20 -08:00 |
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Keerthan Jaic
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d682d40e31
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Merge pull request #1 from cogenda/travis_ci
travis-ci: add co-simulation tests.
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2015-02-26 11:22:59 -08:00 |
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Henry Gomersall
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f2049fd860
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Merge remote-tracking branch 'upstream/master'
Merging in upstream master
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2015-02-26 12:56:11 +00:00 |
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Henry Gomersall
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0945697fc8
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Made sure the myhdl VHDL support package is also placed in the desired directory when the directory attribute of toVHDL is set.
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2015-02-26 12:52:00 +00:00 |
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Shen Chen
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870b735f2b
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travis-ci: add co-simulation tests.
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2015-02-26 19:39:46 +08:00 |
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Shen Chen
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09c98e525e
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switch to list-of-command-arguments in cosimulation testcases
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2015-02-26 17:53:26 +08:00 |
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Shen Chen
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87c6a8a1e3
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update docs on Cosimulation(exe, ...)
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2015-02-26 17:52:46 +08:00 |
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Shen Chen
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f0a98965ba
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cosim: simulator command line (exe) may contain arguments with spaces. Use a list of string, each for an argument, in this case.
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2015-02-26 16:32:20 +08:00 |
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Keerthan Jaic
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ffd01a5eac
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remove 'import exceptions'
It does not need to be imported manually
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2015-02-25 20:52:55 -08:00 |
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Keerthan Jaic
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2894164a6d
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_util.py: remove unused imports
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2015-02-25 20:52:36 -08:00 |
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Keerthan Jaic
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78eba1bb37
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fix _convutils references
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2015-02-25 20:52:29 -08:00 |
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Keerthan Jaic
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bbeb992115
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merge util and convutils
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2015-02-25 20:52:12 -08:00 |
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Keerthan Jaic
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2c14cefbcb
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Fix format string for py2.6 compatibility
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2015-02-25 20:52:08 -08:00 |
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Keerthan Jaic
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c2021eb8c7
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Remove unsupported type check in _analyze.py since it is already done in _toVerilog,_toVHDL
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2015-02-25 20:51:53 -08:00 |
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