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Author	SHA1	Message	Date
jand	7ef1dd3370	copied into conversion	2006-09-19 14:37:00 +00:00
jand	605d725a56	conversion dir	2006-09-19 10:09:33 +00:00
jand	c426aa2386	restructured error and warning classes	2006-09-15 21:29:33 +00:00
jand	80c742a99f	error handling	2006-09-15 14:21:58 +00:00
jand	627e8f2e11	redo size inference	2006-09-15 13:46:25 +00:00
jand	f719e27bf7	before intro resize	2006-09-10 20:20:17 +00:00
jand	48c63e0a09	cookbook	2006-09-08 20:34:32 +00:00
jand	03665d67fa	test_dec and py.test	2006-09-08 08:30:37 +00:00
jand	3eccc04e51	loop test vhdl	2006-09-04 20:31:22 +00:00
jand	7935f3e877	added	2006-09-01 16:18:06 +00:00
jand	0ec897431f	HEC test works	2006-09-01 16:03:00 +00:00
jand	89ae9c22e6	fsm test	2006-09-01 12:39:58 +00:00
jand	db816b94ff	bin2gray test works	2006-08-28 18:38:26 +00:00
jand	1b653ac836	version number	2006-08-22 21:06:34 +00:00
jand	b9b3043810	intermediate checkin	2006-08-22 21:05:57 +00:00
jand	72df2389f0	generated verilog	2006-08-21 22:00:46 +00:00
jand	980fb2ab2d	added	2006-08-18 21:13:16 +00:00
jand	7257a6b76b	fsm example	2006-08-14 21:56:49 +00:00
jand	1aa24190e0	added	2006-08-14 21:52:10 +00:00
jand	a26c42185a	boolean operators	2006-07-15 10:23:00 +00:00
jand	3a8b0da47f	add and sub	2006-07-14 20:40:52 +00:00
jand	352dd02c90	working inc	2006-07-13 10:00:17 +00:00
jand	476ca42e3f	moved to core	2006-07-07 14:46:33 +00:00
jand	65f2f59a80	rudimentary conversion verifier test run	2006-07-07 14:41:32 +00:00
jand	e14c01d30a	first VHDL example that works	2006-07-03 21:21:16 +00:00
jand	a6b77fd084	intermediate toVHDL checkin	2006-06-29 08:10:57 +00:00
jand	5a18828ea6	initial VHDL support commit	2006-06-21 19:50:12 +00:00
jand	fa4c961844	typo	2006-05-11 07:57:27 +00:00
jand	f2e1ff2f10	0.5.1	2006-05-01 10:42:39 +00:00
jand	f43ccb3abd	deleted rel_0-5-1	2006-04-27 11:02:38 +00:00
jand	77e2887c47	to 0.5.1	2006-04-27 11:01:34 +00:00
jand	a37de0d825	typo	2006-04-14 13:21:36 +00:00
jand	afaeeaea3a	typo	2006-04-14 13:18:05 +00:00
jand	ddbeea7aa6	0.5.1	2006-04-14 13:13:05 +00:00
jand	685d235740	0.5.1	2006-04-14 13:11:39 +00:00
jand	fc8a93fc7e	adapted to link removal	2006-04-14 10:10:19 +00:00
jand	d881f97f2d	added file as non-link	2006-04-14 10:07:27 +00:00
jand	5bb3b82592	delete link	2006-04-14 10:01:08 +00:00
jand	1d8dbe890d	added	2006-04-14 09:51:07 +00:00
jand	61494f022e	info	2006-04-14 09:31:30 +00:00
jand	dd0a217786	page release	2006-04-13 21:04:11 +00:00
jand	10ebc57d47	delete	2006-04-06 20:45:22 +00:00
jand	c98626e4a8	added	2006-04-06 20:40:30 +00:00
jand	a27a85773c	improvements	2006-04-06 20:37:44 +00:00
jand	1c6daba8b3	cosmetics	2006-04-01 13:19:24 +00:00
jand	355624a43f	type inference with signal .val attribute ... better conversion to bool value in Verilog added edge test to check various possibilities	2006-03-31 20:09:27 +00:00
jand	411dcbe43e	better handling of boolean operator shortcuts ... and boolean variable inference	2006-03-31 19:13:49 +00:00
jand	19a5315773	conversion parameters	2006-03-27 21:37:57 +00:00
jand	2433e2b44a	added	2006-03-27 21:34:56 +00:00
jand	3283b9a663	latex doc up to date with svn	2006-03-27 16:21:21 +00:00