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Author SHA1 Message Date
Nicolas Pinault
93be66168a
Reports range() without parameter 
When using range() without parameter, a cryptic error message is displayed by converter :
  File "xxx.py", line 1275, in visit_For
    start, stop, step = args
ValueError: need more than 0 values to unpack

Replaces it by a useful information message :
raise ConversionError(kind, msg, info)
myhdl.ConversionError: in file xxx.py, line 49:
    Requirement violation: at least one argument requested
 2018-03-01 15:49:55 +01:00
jandecaluwe
80069e7df8
Merge pull request #175 from cfelton/test_interfaces 
Added nested interface test
 2018-02-25 17:55:34 +01:00
jandecaluwe
12dfb9e69f
Merge pull request #54 from udara28/add_tests 
Added two new tests for verifying shadow of shadow signal functionality
 2018-02-25 17:30:45 +01:00
Jan Decaluwe
4702186edd Fix for #210 2018-02-25 17:10:39 +01:00
Christopher
e0d1baa586 Merge remote-tracking branch 'origin/master' into test_interfaces 2018-02-24 09:33:45 -06:00
jandecaluwe
d5683768bf
Merge pull request #232 from hellow554/patch-2 
Update _enum.py
 2018-02-24 11:23:36 +01:00
jandecaluwe
cecc56dc4c
Merge pull request #223 from nfarring/vcd_timescale_1ps 
Added support for picosecond resolution in VCD trace files.
 2018-02-24 11:21:26 +01:00
jandecaluwe
e318032bec
Merge pull request #227 from hellow554/patch-1 
Changed backup vcd filename creation
 2018-02-24 11:08:43 +01:00
jandecaluwe
e4b27959d3
Merge pull request #211 from serpis/fix_traceSignals 
Fix signal trace for array-of-enums
 2018-02-23 22:14:14 +01:00
jandecaluwe
6f80dac0c7
Merge pull request #189 from hgomersall/improved_block_mk2 
[FIX] fixed a couple of issues with the way classes are handled by the new block decorator
 2018-02-23 21:59:39 +01:00
jandecaluwe
e2dac1c6d0
Merge pull request #194 from josko7452/josko7452/fix_issue_185 
[FIX] Declare signal procedure parameters as signals
 2018-02-23 21:37:56 +01:00
jandecaluwe
8d18a7a371
Merge pull request #186 from Vikram9866/issue185 
Added test for issue_185
 2018-02-23 21:27:30 +01:00
jandecaluwe
f66a48c83e
Merge pull request #188 from josko7452/josko7452/verilog-vhdl-instance-in-block 
Add vhdl_/verilog_instance to _Block decorator
 2018-02-23 21:08:40 +01:00
Henry Gomersall
c6818e2dd9
Added a blank line to kick travis into rerunning the tests now it has been fixed. 2018-02-23 13:49:34 +00:00
udara28
096bad03a5 Adding two tests for verifying shadow signal functionality after merging with latest master 2018-02-22 11:24:08 -05:00
udara28
d726752437 Merge branch 'master' of https://github.com/jandecaluwe/myhdl into add_tests 2018-02-22 11:21:09 -05:00
jandecaluwe
4553fdd5e7
Merge pull request #160 from MrCanadianMenace/name_collision_fix 
[RDY] Name collision fix (Issue #95)
 2018-02-22 08:43:38 +01:00
Jan Decaluwe
20e67ff6e5 devil in detailsss 2018-02-21 22:21:01 +01:00
Jan Decaluwe
ab8c802aa1 try another fix 2018-02-21 22:07:51 +01:00
Jan Decaluwe
5abf86d329 try to fix ghdl path for travis 2018-02-21 21:34:04 +01:00
jandecaluwe
212792f98a
Merge pull request #159 from atharvaw/master 
Increasing test coverage for encoding in enum
 2018-02-21 21:00:19 +01:00
Henry Gomersall
bf3d14a7bb
Cleaned up the improved block work in order to fix a naming bug on class method blocks. 2017-11-24 10:32:33 +00:00
Henry Gomersall
2371c58288
Merging in upstream changes since original fork. 2017-11-11 11:56:49 +00:00
Marcel Hellwig
08360ad126 Update _enum.py 
removed duplicate str = repr
 2017-06-27 08:15:53 +02:00
Marcel Hellwig
7542a219f8 Update test_traceSignals.py 
Adapted test to new backup filename convention
 2017-05-23 15:36:45 +02:00
Marcel Hellwig
8dc6f96cef Changed backup vcd filename creation 
When there is already a vcd file with the same name, do not just append the timestamp to the filename, but remove the '.vcd' extension, append the timestamp and append the .vcd extension again, so that file will always have the right file extension (very useful for windows systems)
 2017-05-23 10:43:12 +02:00
Nathan Farrington
9e2748968f Added support for picosecond resolution in VCD trace files. 
- Added optional timescale parameter to _Block.config_sim()
  - Default value is '1ns'
- Forward timescale parameter to traceSignals() call.
- Added code to _traceSignals.py to use optional timescale keyword arg.
- Checked that both '1ns' and '1ps' show up correctly in VCD trace file.
 2017-05-02 11:37:59 -07:00
jandecaluwe
29069ae477 Merge pull request #200 from hgomersall/initial_value_support 
[FIX] fixed initial value support for bool lists and list of wires
 2017-04-09 10:20:07 +02:00
jandecaluwe
1794e952f0 Merge branch 'master' into initial_value_support 2017-04-09 10:04:02 +02:00
jandecaluwe
8ca7a87fbd Merge pull request #193 from hgomersall/single_bit_vhdl_representation 
[FIX] Tests and fix for VHDL conversion of if/elif/else->case statements for boolean signals
 2017-04-09 09:08:20 +02:00
jandecaluwe
dc187e244c Merge pull request #184 from rqou/multiple_cosim 
Remove the limitation to have only one cosimulation
 2017-04-09 09:06:36 +02:00
Keerthan Jaic
eb4771d280 Merge pull request #170 from srivatsan-ramesh/master 
Added test for issue_169
 2017-03-27 19:04:38 -04:00
Jakob Fries
48b2ee5f0a Fix signal trace for array-of-enums 2017-01-20 08:53:36 +01:00
Henry Gomersall
1ef545af9f
[FIX] Fixed the naming of class method blocks, removing the chance of name collision. 2017-01-19 17:41:14 +00:00
Keerthan Jaic
a56544b6e3 travis: add python 3.6 2017-01-12 11:23:28 -05:00
Keerthan Jaic
393c650b0e update travis badge in readme 2016-12-08 16:43:50 -05:00
jandecaluwe
3736028243 Update README.md 2016-11-30 16:28:36 +01:00
Henry Gomersall
a8a871d520
[FIX] fixed the initial value case under Verilog where a list of signals are wires. 2016-11-23 19:04:46 +00:00
jandecaluwe
1891a2a886 Merge pull request #197 from jck/travis 
Travis improvements
 2016-11-23 18:12:58 +01:00
Henry Gomersall
5e80435513
Merge remote-tracking branch 'upstream/master' into initial_value_support 2016-11-04 16:32:54 +00:00
Henry Gomersall
498b0b3a52
FIX: Corrected list of bools initial value support in VHDL. 2016-11-04 16:27:08 +00:00
Keerthan Jaic
71f5ff1490 travis: move simulator installation to before_script 2016-10-24 23:44:15 -04:00
Keerthan Jaic
f803c1fd8b travis: install simulator only when needed 2016-10-24 23:38:51 -04:00
Keerthan Jaic
af2b4cb041 travis: use new trusty build environment 
https://docs.travis-ci.com/user/trusty-ci-environment/
 2016-10-24 23:38:15 -04:00
Keerthan Jaic
f54ff1a28a travis: install ghdl only if CI_TARGET is ghdl 2016-10-24 23:37:37 -04:00
Keerthan Jaic
7e25d9dc26 travis: remove commented out allowed failures 2016-10-24 23:37:37 -04:00
Bruno Kremel
23d8fc334f Declare signal procedure parameters as signals 
To fix issue 185 we need to declare procedure parameters
as signals if they are signals.
 2016-09-06 09:48:19 +02:00
Patrick Egan
62e1fb9a54 Fixed object being passed to _nameValidate 2016-09-02 17:30:38 -04:00
Patrick Egan
0d6a5d78d0 made import statement in _toVHDL.py more specific and fixed warning in _VHDLNameValidation 2016-09-02 15:45:03 -04:00
Patrick Egan
7f31b570f7 Fixed _VHDLNameValidation.py method calls in _toVHDL.py 2016-09-01 23:57:03 -04:00