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97 Commits

Author SHA1 Message Date
Jan Decaluwe
62675e6a80 manual update 2016-06-20 18:59:39 +02:00
Jan Decaluwe
5e1045ef9b conversion examples 2016-05-23 16:11:01 +02:00
Jan Decaluwe
7f068bb0ea Review and update unittest chapter 2016-05-22 14:01:58 +02:00
Jan Decaluwe
5c8fe79296 Revise unittest chapter 2016-05-20 11:31:04 +02:00
Jan Decaluwe
37955746f7 Modernize bin2gray; also fix trace setting in hierarchy 2016-05-18 22:29:58 +02:00
Jan Decaluwe
095eb040e7 Rewrote chapter completely, example code snippets only 2016-05-18 14:17:25 +02:00
Jan Decaluwe
f272f8fba4 Use myhdldoctools instead of doctest 2016-05-11 21:02:34 +02:00
Jan Decaluwe
d1fa460311 Update first part of the manual 2016-03-22 18:09:38 +01:00
Keerthan Jaic
038310d95a docs: custom directive for including/running examples 2016-03-15 18:32:11 -04:00
srivatsansoft
8e69e0f334 updated doc for the new public method sim.quit() 2016-03-03 07:46:19 +05:30
Marcel Hellwig
ea6cba2f40 Add 'filename' attribute to traceSignals 2016-01-30 20:17:01 +01:00
Nic McDonald
94bc28f076 Add 'directory' attribute to traceSignals. 
This change does exactly what the 'directory' attribute for toVerilog and toVHDL
do. It allows the user to specify the output directory for VCD files.

This commit includes the source change, documentation change, and a py.test
change to test the functionality.
 2016-01-24 22:17:37 -08:00
Jan Decaluwe
44635e7132 Streamlined interface documentation 2015-07-08 09:30:44 +02:00
Jan Decaluwe
2d6be545a7 Doc for std_logic_ports 2015-07-08 08:44:45 +02:00
Jan Decaluwe
0ede42417f Doc update for ConcatSignal 2015-07-07 10:06:31 +02:00
Christopher Felton
6c65f973b6 cleaned up a conversion example, removed unused code 2015-03-25 07:57:24 -05:00
Shen Chen
87c6a8a1e3 update docs on Cosimulation(exe, ...) 2015-02-26 17:52:46 +08:00
Christopher Felton
1513a24e18 Updated 0.9 documentation. 
Updated the MyHDL manual to include the 0.9 what's new in the
index and additional verbage in the conversion section on
interfaces.  This commit is also being used as a test vehicle
for the new development flow using git.
 2015-02-22 18:52:09 -06:00
Henry Gomersall
f83dbe835d Added tests, code and docs to implement directory setting for toVHDL and toVerilog. 
--HG--
branch : 0.9-dev-set_file_dir
 2015-02-18 20:38:49 +00:00
Henry Gomersall
1511dd6de0 Simplified the mux doctest to only have one copy of the code. 
--HG--
branch : 0.9-dev
 2015-01-09 11:14:35 +00:00
Henry Gomersall
346cafa374 Added the FSM in rtl.rst to the doctest code. 
--HG--
branch : 0.9-dev
 2015-01-04 17:21:09 +00:00
Henry Gomersall
b540d4608c Set the correct initialisation value for the FSM example in docs. 
--HG--
branch : 0.9-dev
 2015-01-04 16:40:04 +00:00
Henry Gomersall
0230cdccfa corrected False to be a synchronous reset in the reference docs 
--HG--
branch : 0.9-dev
 2015-01-04 16:35:29 +00:00
Henry Gomersall
72c8ebdf97 Fixed up the doctest code in rtl.rst to pass the tests. 
--HG--
branch : 0.9-dev
 2015-01-04 16:28:47 +00:00
Christopher Felton
71be1466de initial doctest commit 2014-05-24 07:43:50 -05:00
Sven-Hendrik Haase
a57a44f83a Fix docs, this is actually just 3 variables 
--HG--
branch : /fix-docs-this-is-actually-just-3-variabl-1397165148577
 2014-04-10 21:26:05 +00:00
Jan Decaluwe
120537ff0a Fixes for readthedocs 2014-04-08 17:51:37 +02:00
Jan Decaluwe
91891cea4b doc ref fixes 2013-05-20 18:06:20 +02:00
Jan Decaluwe
46047f92d9 doc fixes 2013-05-20 12:41:30 +02:00
Jan Decaluwe
41ee7bb219 0.8 doc improvements 2013-05-16 00:38:14 +02:00
Christopher Felton
2c9ddf1223 fixed indent 
--HG--
branch : 0.8-dev
 2013-05-10 17:01:50 -05:00
Christopher Felton
ec84444352 fixed misformed link 
--HG--
branch : 0.8-dev
 2013-05-10 16:57:18 -05:00
Christopher Felton
db62cc6f2c inadvertatnly removed spaces in an example, spaces added back 
--HG--
branch : 0.8-dev
 2013-05-09 19:02:37 -05:00
Christopher Felton
fa832eb229 spelling corrections 
--HG--
branch : 0.8-dev
 2013-05-09 18:58:55 -05:00
Christopher Felton
c441185e34 updated manaul seq examples with always_seq 
--HG--
branch : 0.8-dev
 2013-05-08 06:02:24 -05:00
Jan Decaluwe
72b40b56a6 Doc for modbv 
--HG--
branch : 0.8-dev
 2013-04-29 09:21:35 +02:00
Jan Decaluwe
7e2fdba7bc doc for other improvements 
--HG--
branch : 0.8-dev
 2013-03-10 22:25:20 +01:00
Jan Decaluwe
f04d53a0fa small corrections 
--HG--
branch : 0.8-dev
 2013-03-10 21:33:26 +01:00
Jan Decaluwe
c9f850508c Factored out hardware-oriented types in separate chapter 
--HG--
branch : 0.8-dev
 2013-03-10 16:35:24 +01:00
Jan Decaluwe
e3879ef878 whatsnew for 0.8 doc, modbv description 
--HG--
branch : 0.8-dev
 2013-03-10 15:48:59 +01:00
Jan Decaluwe
e51da60524 add @always_seq and modbv to conversion examples 
--HG--
branch : 0.8-dev
 2012-12-21 17:08:50 +01:00
Jan Decaluwe
be79683f63 modbv reference info, refactored data types and function sections 
--HG--
branch : 0.8-dev
 2012-12-21 12:57:41 +01:00
Jan Decaluwe
f97a43e72f reference info for @always_seq 
--HG--
branch : 0.8-dev
 2012-12-21 12:34:31 +01:00
Jan Decaluwe
30795da796 reference info for ResetSignal 
--HG--
branch : 0.8-dev
 2012-12-21 12:29:34 +01:00
Jan Decaluwe
9182cadc92 clarified synthesis 
--HG--
branch : 0.8-dev
 2012-05-06 14:59:24 +02:00
Jan Decaluwe
20a9394123 break up the modeling chapter in three 
Mark high level clearly as separate from synthesis

--HG--
branch : 0.8-dev
 2012-05-06 09:59:31 +02:00
Jan Decaluwe
5ad772c4b1 Implemented and documented timescale attribute for VCD output 
--HG--
branch : 0.8-dev
 2012-04-25 21:25:04 +02:00
Günter Dannoritzer
f229fad936 Doc: Added two index entries for 'user-defined code' to the manual. 2011-05-04 20:51:59 +02:00
Jan Decaluwe
9e311a73fe aspell typo check 2010-12-20 10:48:44 +01:00
Jan Decaluwe
78442acc51 Documentation for docstring propagation 2010-12-19 12:28:51 +01:00