* Add initial support for match/case in python, only available in 3.10 on
* Fixed testing so that only the match code is used on python 3.10 or above
* Add spport for enumerated types in match statments
* Rewrote the code to leverage the correct AST way of walking the case/match tree to build the correct RTL versions
* Removed enumerate where not used
* Removed enumerate where not used
* Move appropriate code into match_case definition
* Remove unused defs
* Remove unused defs
* Cleanup of redundant code, and replace some simple variable names with more representative names
* Move conditional so the whole job doesn't run unless it is a tag
* Add dist to make and restructure release
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add message
* Add README to release to appear on PyPi
* Added read definition
* Clean up verify convert warnings
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)
* Fixed all tests to handle the analyze/verify deprecation
* Fixed to catch the correct error, List of signals as a port is not supported
* Add a way to search for and add myhdl.vpi
* Add explict test to check for deprecation case
* Change warning from UserWarning (which is the default) to DeprecationWarning
* Change test operation from script to makefile
* No longer use travis
* Add some ANSI colored logging
* Fixed test to look for DeprecationWarning
* Add lining step
* Add linting step
* Add linting step
* Remove matrix step
* Add work/ to clean list
* Hide echo commands in window
* The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks
* Add myhdl.vpi to clean
* Mark these tests as xfail, for now,
* Fix and unmark xfail 2 tests
* Add black support
* Remove python2 only testing
* Need to relook at this test, it performs differently for verilog and vhdl
* Add RTL files to the list
* Need to relook at this test, it performs differently for verilog and vhdl
* Upgrade to DeprecationWarnings
* Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged
* Add more examples for the Deprecation cases, toVHDL and toVerilog
* Fix deprecations catching
* Fix pytest to use pytest.ini
* Add pypi release steps
* Fix intbv error
* Fix indent
* Update to do a release
* Add checkout to step
* Update Python versions
* Add dependancy on tag on push
