1
0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00

58 Commits

Author SHA1 Message Date
Dave Keeshan
3775119f83
Clean PyPi release flow 17/12/2022 (#399)
* Move conditional so the whole job doesn't run unless it is a tag

* Add dist to make and restructure release

* Add message

* Add message

* Add message

* Add message

* Add message

* Add message

* Add message

* Add message

* Add message

* Add README to release to appear on PyPi

* Added read definition
2022-12-18 20:30:27 +01:00
Dave Keeshan
f8022d3dbd
Update makeflow (#396)
* Clean up verify convert warnings

* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)

* Rewrote test and remove Xfail, test is passing now (is it supposed to fail?)

* Fixed all tests to handle the analyze/verify deprecation

* Fixed to catch the correct error, List of signals as a port is not supported

* Add a way to search for and add myhdl.vpi

* Add explict test to check for deprecation case

* Change warning from UserWarning (which is the default) to DeprecationWarning

* Change test operation from script to makefile

* No longer use travis

* Add some ANSI colored logging

* Fixed test to look for DeprecationWarning

* Add lining step

* Add linting step

* Add linting step

* Remove matrix step

* Add work/ to clean list

* Hide echo commands in window

* The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks

* Add myhdl.vpi to clean

* Mark these tests as xfail, for now,

* Fix and unmark xfail 2 tests

* Add black support

* Remove python2 only testing

* Need to relook at this test, it performs differently for verilog and vhdl

* Add RTL files to the list

* Need to relook at this test, it performs differently for verilog and vhdl

* Upgrade to DeprecationWarnings

* Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged

* Add more examples for the Deprecation cases, toVHDL and toVerilog

* Fix deprecations catching

* Fix pytest to use pytest.ini

* Add pypi release steps

* Fix intbv error

* Fix indent

* Update to do a release

* Add checkout to step

* Update Python versions

* Add dependancy on tag on push
2022-12-17 13:21:08 +01:00
Hugo
81c76f3a52 Add python_requires to help pip 2019-03-12 17:57:19 +02:00
Hugo
562aa3a409 Drop support for legacy Python 2.7 2019-03-12 17:51:12 +02:00
Keerthan Jaic
6ae7969935 remove download_url since pip does not use it by default anymore 2015-03-29 13:23:34 -04:00
Keerthan Jaic
f93ab22e0e distribute cosim source code with package
the source code will be put in sys.prefix/share/myhdl/cosimulation.
sys.prefix will be /usr or /usr/local for global install, or root dir of
virtualenv.

This has two benifits:
1. Distro packages/pip installs will come with the cosim source code, so
   users don't need to clone the git repo.
2. Tools can easily automate compilation of the cosimulation vpis.

fixes jck/uhdl#2
2015-03-29 13:23:27 -04:00
Keerthan Jaic
c673f1c1c5 deduplicate version info 2015-03-29 06:42:09 -04:00
Keerthan Jaic
db677326eb clean up setup.py
* Prefer setuptools over distutils
* Extend version checking to disallow python 3.0 to 3.3
* Add python version classifiers
2015-03-29 06:42:09 -04:00
Keerthan Jaic
d373c4e278 Fix print statements in setup.py 2015-03-11 08:07:50 -04:00
Henry Gomersall
1ee356c6b4 Merging in mainline.
--HG--
branch : 0.9-dev-doctest
2015-02-11 15:56:38 +00:00
Henry Gomersall
7a5b6fc0ff Merged with mainline.
--HG--
branch : 0.9-dev
2015-01-04 17:27:08 +00:00
Jan Decaluwe
050d3f1917 Fix download url 2014-08-26 10:59:59 +02:00
Jan Decaluwe
1903677a56 status 2014-08-26 10:06:55 +02:00
Jan Decaluwe
4189d9ba95 Bug fix merge from default
--HG--
branch : 0.9-dev
2013-09-15 22:36:59 +02:00
Jan Decaluwe
cb82cad878 version number 2013-09-15 22:34:40 +02:00
Jan Decaluwe
41ee7bb219 0.8 doc improvements 2013-05-16 00:38:14 +02:00
Jan Decaluwe
aa70757209 Version number 0.8
--HG--
branch : 0.8-dev
2013-05-13 17:16:44 +02:00
Jan Decaluwe
9eacce1ebb added draft implementation of modbv.py and corresponding benchmark updates
--HG--
branch : 0.8-dev
2011-05-21 13:33:25 +02:00
Jan Decaluwe
4915a896e0 Prepare _intbv for subclassing
--HG--
branch : 0.8-dev
2011-05-21 09:19:41 +02:00
Jan Decaluwe
52814f1eb3 Version number 0.7 2010-12-19 18:20:35 +01:00
Jan Decaluwe
75d85e4b98 setup 0.7dev in default branch 2009-04-25 16:51:01 +02:00
Jan Decaluwe
7255653ed2 version number 0.6 2008-12-21 15:42:55 +01:00
Jan Decaluwe
ce3e8c00b2 Updated copyright notice, removed keyword expansion symbols 2008-12-02 11:08:08 +01:00
Jan Decaluwe
1697a4fab0 prepare for development release 2008-08-21 15:29:10 +02:00
jand
47fa6fc544 Solved bug related to bit inversion ins expressions
when converted to VHDL
2008-03-27 16:52:40 +00:00
jand
32f75dd80b support for min and max attribute conversion 2008-01-30 08:53:53 +00:00
jand
77a0d8c1d4 conversion bug from IPROBE project 2007-12-20 13:53:23 +00:00
jand
d30bac487d 0.6dev5 setup 2007-06-28 20:45:16 +00:00
jand
9b92962595 move to 0.6dev4
fix custom Verilog test
2007-01-12 21:37:43 +00:00
jand
39a2603d92 augmented assigns 2006-11-07 11:57:26 +00:00
jand
cd72fbb29f ram 2006-10-12 20:32:06 +00:00
jand
e5d346b79d manifest 2006-10-04 15:28:04 +00:00
jand
bc8aa99816 version number 2006-10-04 15:15:32 +00:00
jand
77e2887c47 to 0.5.1 2006-04-27 11:01:34 +00:00
jand
d96efbcb3f before going to svn 2006-03-08 16:04:18 +00:00
jand
fb3b4393bc 0.5 2005-12-27 16:55:12 +00:00
jand
a351bf27a2 0.5c1 2005-12-27 14:48:54 +00:00
jand
e06395abe6 beta 2005-12-19 13:00:25 +00:00
jand
93440598e9 error reporting with user defined verilog 2005-11-22 21:00:48 +00:00
jand
f707d0024a dev5 2005-11-21 11:07:14 +00:00
jand
26a43394c4 user-defined verilog
bug fixes with hierarchical naming
2005-11-13 21:09:42 +00:00
jand
acc510f5ba signed arithmetic 2005-11-04 09:07:13 +00:00
jand
0e564e672d decorators 2005-10-21 09:37:50 +00:00
jand
2584fa6b59 at least 2.4 2005-10-06 20:08:06 +00:00
jand
b4b6415a34 0.4.1 2004-03-03 09:56:04 +00:00
jand
b4057b2ee7 toVerilog package 2004-02-04 17:13:07 +00:00
jand
0acccaa497 0.4 2004-01-07 21:36:05 +00:00
jand
7d68a65274 0.4 2004-01-07 21:28:04 +00:00
jand
7ce730cb30 adapted for register 2003-09-08 07:45:10 +00:00
jand
3464205194 new version 2003-09-08 07:15:41 +00:00