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Author SHA1 Message Date
Marcel Hellwig
08360ad126 Update _enum.py 
removed duplicate str = repr
 2017-06-27 08:15:53 +02:00
Marcel Hellwig
7542a219f8 Update test_traceSignals.py 
Adapted test to new backup filename convention
 2017-05-23 15:36:45 +02:00
Marcel Hellwig
8dc6f96cef Changed backup vcd filename creation 
When there is already a vcd file with the same name, do not just append the timestamp to the filename, but remove the '.vcd' extension, append the timestamp and append the .vcd extension again, so that file will always have the right file extension (very useful for windows systems)
 2017-05-23 10:43:12 +02:00
Nathan Farrington
9e2748968f Added support for picosecond resolution in VCD trace files. 
- Added optional timescale parameter to _Block.config_sim()
  - Default value is '1ns'
- Forward timescale parameter to traceSignals() call.
- Added code to _traceSignals.py to use optional timescale keyword arg.
- Checked that both '1ns' and '1ps' show up correctly in VCD trace file.
 2017-05-02 11:37:59 -07:00
jandecaluwe
29069ae477 Merge pull request #200 from hgomersall/initial_value_support 
[FIX] fixed initial value support for bool lists and list of wires
 2017-04-09 10:20:07 +02:00
jandecaluwe
1794e952f0 Merge branch 'master' into initial_value_support 2017-04-09 10:04:02 +02:00
jandecaluwe
8ca7a87fbd Merge pull request #193 from hgomersall/single_bit_vhdl_representation 
[FIX] Tests and fix for VHDL conversion of if/elif/else->case statements for boolean signals
 2017-04-09 09:08:20 +02:00
jandecaluwe
dc187e244c Merge pull request #184 from rqou/multiple_cosim 
Remove the limitation to have only one cosimulation
 2017-04-09 09:06:36 +02:00
Keerthan Jaic
eb4771d280 Merge pull request #170 from srivatsan-ramesh/master 
Added test for issue_169
 2017-03-27 19:04:38 -04:00
Jakob Fries
48b2ee5f0a Fix signal trace for array-of-enums 2017-01-20 08:53:36 +01:00
Henry Gomersall
1ef545af9f
[FIX] Fixed the naming of class method blocks, removing the chance of name collision. 2017-01-19 17:41:14 +00:00
Keerthan Jaic
a56544b6e3 travis: add python 3.6 2017-01-12 11:23:28 -05:00
Keerthan Jaic
393c650b0e update travis badge in readme 2016-12-08 16:43:50 -05:00
jandecaluwe
3736028243 Update README.md 2016-11-30 16:28:36 +01:00
Henry Gomersall
a8a871d520
[FIX] fixed the initial value case under Verilog where a list of signals are wires. 2016-11-23 19:04:46 +00:00
jandecaluwe
1891a2a886 Merge pull request #197 from jck/travis 
Travis improvements
 2016-11-23 18:12:58 +01:00
Henry Gomersall
5e80435513
Merge remote-tracking branch 'upstream/master' into initial_value_support 2016-11-04 16:32:54 +00:00
Henry Gomersall
498b0b3a52
FIX: Corrected list of bools initial value support in VHDL. 2016-11-04 16:27:08 +00:00
Keerthan Jaic
71f5ff1490 travis: move simulator installation to before_script 2016-10-24 23:44:15 -04:00
Keerthan Jaic
f803c1fd8b travis: install simulator only when needed 2016-10-24 23:38:51 -04:00
Keerthan Jaic
af2b4cb041 travis: use new trusty build environment 
https://docs.travis-ci.com/user/trusty-ci-environment/
 2016-10-24 23:38:15 -04:00
Keerthan Jaic
f54ff1a28a travis: install ghdl only if CI_TARGET is ghdl 2016-10-24 23:37:37 -04:00
Keerthan Jaic
7e25d9dc26 travis: remove commented out allowed failures 2016-10-24 23:37:37 -04:00
Bruno Kremel
23d8fc334f Declare signal procedure parameters as signals 
To fix issue 185 we need to declare procedure parameters
as signals if they are signals.
 2016-09-06 09:48:19 +02:00
Patrick Egan
62e1fb9a54 Fixed object being passed to _nameValidate 2016-09-02 17:30:38 -04:00
Patrick Egan
0d6a5d78d0 made import statement in _toVHDL.py more specific and fixed warning in _VHDLNameValidation 2016-09-02 15:45:03 -04:00
Patrick Egan
7f31b570f7 Fixed _VHDLNameValidation.py method calls in _toVHDL.py 2016-09-01 23:57:03 -04:00
Patrick Egan
e11125a07a Removed class structure and fixed errors related to .lower() usage 2016-09-01 12:01:02 -04:00
Patrick Egan
1520d995c1 Fixed analyze import problem and updated .gitignore to exclude pycharm configuration files 2016-09-01 01:51:25 -04:00
Henry Gomersall
4f8ef24fdf
[BUGFIX] Tests and fix for VHDL conversion of if/elif/else->case statements for boolean signals 2016-08-25 16:17:48 +01:00
Henry Gomersall
ab4a08c3aa
Fixed problem with setting vhdl_code and verilog_code on class methods and added test. 2016-08-04 18:37:30 +01:00
Bruno Kremel
f19f1e3caf Add vhdl_/verilog_instance to _Block decorator 2016-08-04 14:37:02 +02:00
vikram9866
0ec0cf7e94 added issue 185 2016-07-18 18:10:43 +05:30
jandecaluwe
310abe82ce Merge pull request #182 from rqou/fix_print_for_real 
Correctly fix _makeAST to preserve future flags
 2016-07-18 07:50:10 +02:00
Robert Ou
aef94df824 Remove the limitation to have only one cosimulation 2016-07-17 17:24:45 -07:00
Robert Ou
d64ebb4377 Correctly fix _makeAST to preserve future flags 
Examines the actual feature flags in use when compiling the function f
and passes those flags to compile(). Fixes #179.
 2016-07-17 16:00:38 -07:00
Jan Decaluwe
1761fc2a0e Use compile instead of ast.parse() so that future flags can be passed #179 
To my suprize, explitly passing the future flags was not required;
apparently the dont_inherit argument is different for ast.parse()
 2016-07-17 17:45:06 +02:00
Jan Decaluwe
d5501698cc Try to get stable results with converts #176 2016-06-23 19:09:26 +02:00
Jan Decaluwe
0727f76a9d Merge branch 'master' of github.com:jandecaluwe/myhdl 
Conflicts:
	myhdl/conversion/_toVerilog.py
 2016-06-20 19:13:39 +02:00
Jan Decaluwe
62675e6a80 manual update 2016-06-20 18:59:39 +02:00
jandecaluwe
f4fde1c9dc Merge pull request #150 from hgomersall/initial_value_support 
Initial value support
 2016-06-19 21:47:26 +02:00
jandecaluwe
edd385646d Merge pull request #174 from josyb/WinCoSim 
CoSimulation on Windows
 2016-06-19 21:13:08 +02:00
Christopher Felton
e2f559c883 use the Block methods and code cleanup 2016-06-03 11:05:05 -05:00
Josy Boelen
6a82b0d4a0 Tidied up a left-over 'print' 2016-06-02 20:29:49 +02:00
Christopher Felton
6999886051 added nested interface to the interface test 2016-06-02 12:45:28 -05:00
Josy Boelen
7f0282c026 _Cosimulation.py: changed split of 'exe' specification 
_compat.py: corrected SetHandleInformation invocation
_verify.py: added -2008 option to 'vcom' to recognise new 'to_hstring' function
test/core/test_Cosimulation.py: reworked 'file handle to file descriptor' extraction under WIndows
 2016-06-01 21:50:49 +02:00
Patrick Egan
acbe257c85 Fixed type error in for loops 2016-05-30 00:10:41 -04:00
Henry Gomersall
4b4be7be6c
Merge remote-tracking branch 'upstream/master' into initial_value_support 2016-05-27 18:25:38 +01:00
Henry Gomersall
0b87349dc0
Removed redundant print statement in VHDL conversion. 2016-05-27 12:52:43 +01:00
srivatsansoft
c8e0dce0c7 Added test for issue 169 2016-05-24 23:03:33 +05:30