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Author SHA1 Message Date
Jan Decaluwe
a4924c207d Migrate a test 2016-02-09 16:39:34 +01:00
Jan Decaluwe
cd964f9540 Migrate a test 2016-02-09 16:34:21 +01:00
Jan Decaluwe
7b615eda1f Migrate a test 2016-02-09 16:31:39 +01:00
Jan Decaluwe
60fd1b44d4 Migrate a test 2016-02-09 16:30:51 +01:00
Jan Decaluwe
4ed840acf2 Migrate a test 2016-02-09 15:15:55 +01:00
Jan Decaluwe
ac682de3cc Migrate a test 2016-02-09 13:50:02 +01:00
Jan Decaluwe
97daf62e1b Infer namespaces for ModuleInstance objects 2016-02-09 13:47:54 +01:00
Jan Decaluwe
a67b3a314e simplify symdict inference 2016-02-08 16:27:45 +01:00
Jan Decaluwe
74520ba900 Also check that module is called in module context 2016-02-08 15:04:24 +01:00
Jan Decaluwe
9cc384835a Migrate interface checks 2016-02-05 16:20:39 +01:00
Jan Decaluwe
a7548cb592 Migrate interfaces test; infer interface only after signal analysis 2016-02-05 14:18:19 +01:00
Jan Decaluwe
9ba5d1ba34 Add decorator signal args to siglist 2016-02-04 21:31:32 +01:00
Jan Decaluwe
2607e1d525 migrate bitonic 2016-02-03 20:45:26 +01:00
Jan Decaluwe
4f2a1df112 Move and migrate test so VHDL sees it also 2016-02-03 17:25:57 +01:00
Jan Decaluwe
378c4f5a3b Migrate test; remove instance count reset; adapt hierarchy traversal 2016-02-03 17:25:57 +01:00
Jan Decaluwe
71337668d5 Add type error check on new interface 2016-02-03 17:25:57 +01:00
Jan Decaluwe
30c1b01194 Add some sophistication to visitor 2016-02-03 17:25:57 +01:00
Jan Decaluwe
becb7a4cff Initial module decorator support 2016-02-03 17:25:57 +01:00
Jan Decaluwe
755d2b8c13 Fix bitonic example; skip locals in AttrRefResolver 2016-02-03 17:24:23 +01:00
Jan Decaluwe
a48eb2e4ca Factor visitor traversal out to top class 2016-01-31 12:15:18 +01:00
Jan Decaluwe
f5de3b3af4 Reuse ast property 2016-01-31 11:52:04 +01:00
Jan Decaluwe
eb821e48c5 Correct error message 2016-01-31 10:44:42 +01:00
Jan Decaluwe
4509e56323 Cleaner interface 2016-01-31 10:31:10 +01:00
Jan Decaluwe
510c532782 Removed unused code and attributes 2016-01-31 10:09:06 +01:00
Jan Decaluwe
b1121a025d Refactor 2016-01-30 20:30:11 +01:00
Jan Decaluwe
710821d5d6 Refactor 2016-01-30 16:39:57 +01:00
Jan Decaluwe
333928b810 removed unused imports 2016-01-30 12:21:20 +01:00
Jan Decaluwe
6f3808fc68 Take this out. No idea what it was supposed to do. 2016-01-30 09:23:03 +01:00
Jan Decaluwe
82f43f056d Remove unused variable 2016-01-30 08:00:39 +01:00
Jan Decaluwe
1971a56a5c sensible default 2016-01-28 12:47:22 +01:00
Jan Decaluwe
75d53cdadb Removed unused code 2016-01-28 12:32:44 +01:00
jandecaluwe
1f960db066 Merge pull request #144 from nicmcd/master 
Add 'directory' attribute to traceSignals.
 2016-01-26 16:38:20 +01:00
Nic McDonald
94bc28f076 Add 'directory' attribute to traceSignals. 
This change does exactly what the 'directory' attribute for toVerilog and toVHDL
do. It allows the user to specify the output directory for VCD files.

This commit includes the source change, documentation change, and a py.test
change to test the functionality.
 2016-01-24 22:17:37 -08:00
jandecaluwe
fb70bb2fc4 Merge pull request #137 from nturley/master 
fix bug in test_custom tests
 2015-11-29 11:51:19 +01:00
jandecaluwe
480d228236 Merge pull request #135 from nturley/patch-1 
add test for issue 134
 2015-11-29 11:47:59 +01:00
nturley
bb2ba3c954 fix bug in test_custom tests 2015-11-15 23:50:34 -06:00
nturley
d60568ae65 fix additional issues with test_issue134 
we only need to analyze. Verify will still fail even with the fix
 2015-11-07 22:21:50 -06:00
nturley
8cc5f23dcb fix test 134 
wrong number and add xfail
 2015-11-07 21:53:35 -06:00
nturley
ed9d2a9e90 add test for issue 134 
checks for port name collision when a function names two signals with the same name
 2015-11-07 21:08:38 -06:00
Jan Decaluwe
9dffa04130 Merge branch '0.9-maintenance' 2015-11-01 21:02:07 +01:00
jandecaluwe
b726eb8139 Merge pull request #133 from clade/0.9-maintenance 
assign statement (constwires) support litterals larger than 32 bits
 2015-11-01 20:59:29 +01:00
Jan Decaluwe
65e6355e11 Added parenthesis to print 2015-11-01 20:32:19 +01:00
Jan Decaluwe
97c8c8ac7d Improve on large constant wires in VHDL 
Triggered by an reported issue with Verilog that
I was not able to reproduce (issue 133).
 2015-10-30 20:38:33 +01:00
Pierre Cladé
ff5b0b1963 assign statement (constwires) support litterals larger than 32 bits 2015-10-29 19:03:14 +01:00
Jan Decaluwe
97dd4e3767 Remove allowed failures 2015-10-25 16:54:08 +01:00
Jan Decaluwe
cb06b1eb88 Remove broken tests - revisit writing to file in conversion later 2015-10-25 16:45:10 +01:00
Jan Decaluwe
69a0e2e5ef Really test function without return value 2015-10-25 16:33:28 +01:00
Jan Decaluwe
107e0e0c1e Return intbv instead of an intbv subclass for certain methods 
In this way, no requirement is implicitly assumed for the
interface of the subclass.
 2015-10-25 15:39:17 +01:00
Jan Decaluwe
385e82dd7e Support negative values in ConcatSignal contributors 2015-10-10 20:20:29 +02:00
jandecaluwe
bd0cfba9a7 Merge pull request #130 from jck/py35 
Python 3 fixes, test improvements
 2015-10-07 20:23:12 +02:00