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Author SHA1 Message Date
Jan Decaluwe
14469e084e merge from default 
--HG--
branch : 0.9-dev
 2014-03-16 20:25:48 +01:00
Jan Decaluwe
bc782464c9 Link to main site in docs 2014-03-16 20:24:16 +01:00
punkkeks
4124e55a76 When using a tristate-driver as 'local variable' in a device and having a reset function, the init value will be None - that's right so far. But when converting this to verilog (maybe vhdl too) the output will be None, which is wrong, it should be 'bz. 
This should fix it at least for verilog. I think the same thing has to be done for vhdl as well.

--HG--
branch : punkkeks/when-using-a-tristatedriver-as-local-var-1390504597923
 2014-01-23 19:16:55 +00:00
Christopher Felton
85f037f97e new interface conversion test needed prints 
--HG--
branch : 0.9-dev
 2014-01-20 18:32:25 -06:00
Christopher Felton
eec15fc6a2 more interface (MEP107) tests 
--HG--
branch : 0.9-dev
 2013-11-17 19:46:31 -06:00
Keerthan Jaic
eae37779f9 VCD Extension for verilog dumpfile 
--HG--
branch : upstream
 2013-10-24 23:38:25 -04:00
Jan Decaluwe
a8949f771f Merge from default 
--HG--
branch : 0.9-dev
 2013-10-16 22:43:05 +02:00
Jan Decaluwe
a22bb76cc2 Added missing file 2013-10-16 22:42:16 +02:00
Jan Decaluwe
e90995a6ba Updated jck's pull request up to 70f83a 
--HG--
branch : 0.9-dev
 2013-10-16 22:36:39 +02:00
Keerthan Jaic
5af444703e Regression: toVerilog uses the toVerilog.name as module name again 
--HG--
branch : upstream
 2013-10-10 23:53:22 -04:00
Keerthan Jaic
e7f7d31f72 trace support(dumpfile) for toVerilog 
--HG--
branch : upstream
 2013-10-07 01:31:50 -04:00
Keerthan Jaic
755850246c Added portmap attribute to _toVerilog to simplify cosimulation 
--HG--
branch : upstream
 2013-10-06 16:49:35 -04:00
Keerthan Jaic
20211ae5b6 branch representing current upstream state 
--HG--
branch : upstream
 2014-02-07 01:25:22 -05:00
Keerthan Jaic
761d9a95fd improved handling of name conflicts plus unittest 
--HG--
branch : 0.9-dev
 2013-09-29 20:10:50 -04:00
Keerthan Jaic
4f01bf32d4 Signal attr ref names(after replacing . with _) can conflict with memory names 
and vice versa.

--HG--
branch : 0.9-dev
 2013-09-29 18:55:50 -04:00
Jan Decaluwe
a066e18427 Bug fix merge from default 
--HG--
branch : 0.9-dev
 2013-09-22 19:14:21 +02:00
Jan Decaluwe
b6f1e7fd9f Fixed bug 43 2013-09-22 19:13:22 +02:00
Keerthan Jaic
962dd8afcc refeactored repeated code into _makeName 
--HG--
branch : 0.9-dev
 2013-09-21 20:32:19 -04:00
Keerthan Jaic
bad0346b29 prevent unnecesarily adding _ to signal names 
--HG--
branch : 0.9-dev
 2013-09-21 20:28:11 -04:00
Keerthan Jaic
885a741889 handle possible name conflict after renaming attr refs. 
--HG--
branch : 0.9-dev
 2013-09-16 15:21:37 -04:00
Keerthan Jaic
30a932d5b9 Refactor naming system for attribute references; This fixes naming issue with 
list of signals.

--HG--
branch : 0.9-dev
 2013-09-16 14:53:20 -04:00
Jan Decaluwe
4189d9ba95 Bug fix merge from default 
--HG--
branch : 0.9-dev
 2013-09-15 22:36:59 +02:00
Jan Decaluwe
cb82cad878 version number 2013-09-15 22:34:40 +02:00
Jan Decaluwe
e72f32c60a Fix for bug 42 2013-09-15 20:59:27 +02:00
Jan Decaluwe
c92725fb36 Bug fix merge from default 
--HG--
branch : 0.9-dev
 2013-09-14 12:56:24 +02:00
Jan Decaluwe
bda7504d5e Fixed issue #3 2013-09-14 12:53:53 +02:00
Jan Decaluwe
98c1d44f46 bug fix merge from default 
--HG--
branch : 0.9-dev
 2013-09-14 10:12:12 +02:00
Jan Decaluwe
09e8a6384e enum_encoding declaraion in top-level package 2013-09-14 10:11:46 +02:00
Jan Decaluwe
63b4767a3d rename for consistency 2013-09-14 09:33:42 +02:00
Jan Decaluwe
7e644341e1 bug fix merge from default 
--HG--
branch : 0.9-dev
 2013-09-14 09:25:56 +02:00
Jan Decaluwe
95e103960d Fixed broken handling of top level enum types 2013-09-14 09:24:58 +02:00
Jan Decaluwe
1313e3142a Merge from default 
--HG--
branch : 0.9-dev
 2013-09-13 23:21:52 +02:00
Jan Decaluwe
291dba1b7e Fix for bug 44 2013-09-13 21:34:11 +02:00
Jan Decaluwe
a15ac9bbed Corrected bug suggested by aj1s 2013-09-08 15:12:54 +02:00
Keerthan Jaic
09129dfccf merge from mep107 
--HG--
branch : 0.9-dev
 2013-08-29 13:53:36 -04:00
Keerthan Jaic
af71a817b2 Removed attribute assignment test from toVerilog/test_NotSupported.py 
--HG--
branch : mep107
 2013-08-29 13:49:52 -04:00
Keerthan Jaic
99c157bacc Improved interface inference. 
--HG--
branch : mep107
 2013-08-26 19:57:31 -04:00
Keerthan Jaic
efde61be87 merged with 0.9-dev 
--HG--
branch : mep107
 2013-08-13 17:17:29 -04:00
Christopher Felton
5712cf1905 no dash in version 
--HG--
branch : 0.9-dev
 2013-08-09 00:03:32 -05:00
Keerthan Jaic
c058e9035d Fix for new aug 07 commit which breaks tests. 
--HG--
branch : 0.9-dev
 2013-08-08 21:34:17 -04:00
Keerthan Jaic
409c07ee87 MEP107(Conversion of attribute signal containers) support 
--HG--
branch : 0.9-dev
 2013-08-07 17:49:09 -04:00
Keerthan Jaic
a99b67432f 0.9 dev branch 
--HG--
branch : 0.9-dev
 2013-08-07 17:40:39 -04:00
Keerthan Jaic
d83f6b849c Added support for non-default signal attributes. 
This allows you to subclass Signal, and define additional attributes.
For example, to name bitfields in signals.

--HG--
branch : mep107
 2013-08-07 16:32:08 -04:00
Keerthan Jaic
6413eb2af3 Improved top level interface inference for conversion. 
--HG--
branch : mep107
 2013-08-07 12:42:58 -04:00
Keerthan Jaic
ad9f32f102 Improved method for detecting when not to resolve attributes. Fixes bugs while 
converting Enums, and potential bugs if new signal attributes are added.

--HG--
branch : mep107
 2013-08-07 11:06:14 -04:00
Christopher Felton
dc2a3d0708 started documentation for mep107 changes 
--HG--
branch : mep107
 2013-07-13 22:20:08 -05:00
Christopher Felton
36a72ff813 added a couple more loops to the test 
--HG--
branch : mep107
 2013-07-13 21:14:25 -05:00
Christopher Felton
fc36a503fb commented out print statements in _verify 
--HG--
branch : mep107
 2013-07-13 21:01:47 -05:00
Christopher Felton
8c56ec9dc9 added second interfaces test 
--HG--
branch : mep107
 2013-07-13 20:57:26 -05:00
Christopher Felton
8543e84033 modified the testbench name 
--HG--
branch : mep107
 2013-07-12 08:44:23 -05:00