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Author	SHA1	Message	Date
jand	f707d0024a	dev5 rel_0-5dev5	2005-11-21 11:07:14 +00:00
jand	1c3a13c946	fine-grained signed arithmetic	2005-11-19 15:37:59 +00:00
jand	26a43394c4	user-defined verilog ... bug fixes with hierarchical naming rel_0-5dev4	2005-11-13 21:09:42 +00:00
jand	28258b40ff	custom Verilog code test	2005-11-09 15:42:56 +00:00
jand	acc510f5ba	signed arithmetic rel_0-5dev3	2005-11-04 09:07:13 +00:00
jand	0dd0b8a8a9	proper intbv initialization	2005-10-22 19:19:39 +00:00
jand	df1c7303e5	delay object rel_0-5dev2	2005-10-21 15:01:41 +00:00
jand	2bb55f5e65	we	2005-10-21 09:39:29 +00:00
jand	0e564e672d	decorators	2005-10-21 09:37:50 +00:00
jand	14cc82a27b	always, instance decorator ... always_comb as decorator	2005-10-18 12:08:07 +00:00
jand	8c4408a7b6	0.5 development rel_0-5dev1	2005-10-07 08:24:44 +00:00
jand	80a35851ad	start signed support ... None default value of intbv	2005-10-06 20:08:36 +00:00
jand	2584fa6b59	at least 2.4	2005-10-06 20:08:06 +00:00
jand	f0fe17b639	added clean target	2005-10-03 16:07:46 +00:00
jand	a9969b0e15	new version of cver	2005-10-03 15:49:57 +00:00
jand	6d292f6e19	object files name suffic .o	2005-10-03 15:49:36 +00:00
jand	dd4760d43f	handle leaf generators properly	2005-09-17 19:28:41 +00:00
jand	7c3206da5a	clean up	2005-09-15 15:47:44 +00:00
jand	f28e09ee29	removed special generator handling	2005-09-15 15:45:55 +00:00
jand	29fa0d50b3	start to support signed	2005-09-14 14:19:40 +00:00
jand	395709cae0	simplified hierarchy extraction ... get rid of findInstanceName	2005-09-14 09:25:59 +00:00
jand	7f11aadc89	adapted traceSignals to use func_name	2005-09-09 09:15:25 +00:00
jand	fba110a473	toVerilog is now a callable instance	2005-09-09 09:15:07 +00:00
jand	60d6cc0142	adapted traceSignals to use func_name, like toVerilog	2005-09-09 09:13:07 +00:00
jand	1750cb0f3c	changed toVerilog to use func_name for file naming	2005-09-08 08:18:23 +00:00
jand	78a68234c3	added	2005-08-19 15:13:55 +00:00
jand	333e2042db	Support for mapping tuple of ints to case statements	2005-08-19 15:11:39 +00:00
jand	5a555f32ac	signal names have priority on list of signals	2005-08-17 17:16:01 +00:00
jand	e940e3d213	Support for lists of signals mapping to Verilog mem	2005-08-09 13:50:03 +00:00
jand	4f645619d4	simple always blocks to assign statements ... non-local objects should be signals check	2005-08-05 09:48:59 +00:00
jand	8225583303	memory support	2005-08-01 09:10:39 +00:00
jand	fa4aa9bbd6	added	2005-07-18 12:05:25 +00:00
jand	09309a2c7a	fixed always_comb singleton senslist handling ... make sure signal name equals port name when converting	2005-07-12 10:23:45 +00:00
jand	dc4eed5f90	optimize singleton sensitivity list in always_comb	2005-02-21 21:47:27 +00:00
jand	1c60486bf5	special waiter of always_comb and cosimulation	2005-02-15 21:48:06 +00:00
jand	b1269e9c3c	added waiter infer tests	2005-02-15 18:02:59 +00:00
jand	a12b3ec280	skip non-named function calls during infer	2005-02-15 18:02:44 +00:00
jand	62a52a3087	merged waiter optimization	2005-02-15 17:45:28 +00:00
jand	6f9fbd47dd	removed lines that cause warnings rel_0-4-1 rel-0-4-1	2004-12-29 20:56:13 +00:00
jand	aa004c9ab3	type error message	2004-12-29 20:50:27 +00:00
jand	57bd2dd857	only check for exception instances in yield clauses	2004-12-29 15:56:03 +00:00
jand	74e62edf93	makefiles	2004-12-29 14:16:53 +00:00
jand	5c9a82ebb1	only exclude verilog files in toVerilog test dir	2004-12-29 13:57:50 +00:00
jand	e07dc17734	exclude verilog files	2004-12-29 13:46:27 +00:00
jand	237a6040cc	added	2004-12-28 17:22:00 +00:00
jand	5fef54e6c7	0.4.1	2004-12-28 17:14:39 +00:00
jand	022998dc9c	cver	2004-12-28 17:04:43 +00:00
jand	8a03438c25	latest cver	2004-12-28 17:03:13 +00:00
jand	a0255aba7b	Hide SuspenSimulation exception. ... Make if possible to yield exceptions. They are raised by the simulator at a point where it is safe to resume later, after they have been caught and handled.	2004-12-28 15:09:40 +00:00
jand	6d49890d0d	future statement removed	2004-12-27 12:31:47 +00:00