FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
1,108 Commits 9 Branches 41 Tags
Commit Graph

1108 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jan Decaluwe
ce14fd90af Support for custom file headers 2010-07-05 16:48:52 +02:00
Jan Decaluwe
9c2b13419b Support for string.Template with vhdl_code and verilog_code attributes 2010-07-05 15:24:17 +02:00
Jan Decaluwe
f44fcfebc3 Use signals directly for indexing with __index__ 2010-07-03 19:09:40 +02:00
Jan Decaluwe
62ace46b26 Improve hiearchical handling of ShadowSignals 2010-07-03 15:12:58 +02:00
Jan Decaluwe
1b4e8706b2 support for user-requested instances 2010-07-02 23:20:24 +02:00
Jan Decaluwe
563777f43d added vhdl_code and verilog_code function attribute as alternative to magic variables 2010-07-02 18:03:00 +02:00
Jan Decaluwe
5a2c6a89b4 refactoring 2010-07-02 16:55:02 +02:00
Jan Decaluwe
e4ff6deccf refactoring 2010-07-02 15:12:44 +02:00
Jan Decaluwe
52a5afa8cc example package 2010-07-02 13:25:24 +02:00
Jan Decaluwe
3b4e7dc293 examples 2010-07-02 13:24:04 +02:00
Jan Decaluwe
4cad5a171e Support for conversion of ternary operator. 
They are converted to ternary equivalents in the target HDL.
If possible, they are converted to single line assigns.
Within a process, this will only work with VHDL-2008.
 2010-07-01 19:13:42 +02:00
Jan Decaluwe
1f79dd17f8 prepare _extractHierarchy for further patches 2010-07-01 12:46:21 +02:00
Jan Decaluwe
7c48c2e171 addition doc writing calls 2010-06-29 16:51:46 +02:00
Jan Decaluwe
51c057fbf6 docstrings forwarded to conversion output 
Official docstrings are put on a hopefully logical place,
but unofficial docstrings are also supported. This provides
a way to control which comments go the converted output, and
which don't (i.e. ordinary Python commnents).
 2010-06-29 16:41:13 +02:00
Jan Decaluwe
5fe347ff13 better support for mapping to case statements 2010-06-22 17:46:44 +02:00
Jan Decaluwe
84ee1bd778 fix to only skip docstrings, not other expressions 2010-06-22 15:03:34 +02:00
Jan Decaluwe
02a9b35798 skip doc string for always_comb block inference 2010-06-22 14:40:13 +02:00
Jan Decaluwe
96ad4abbcd docstrings in Verilog output 2010-06-22 13:28:51 +02:00
Jan Decaluwe
1ab5fccce8 support for custom file headers in toVerilog 2010-06-22 11:26:31 +02:00
Jan Decaluwe
69b9225e67 support for optional represention of integer literals has hex numbers 2010-06-22 10:15:48 +02:00
Jan Decaluwe
c61634f759 removed parallel_case / full_case synthesis directives 2010-06-22 09:37:17 +02:00
Jan Decaluwe
9fb95914d5 optional support for blocking assignments only in combinatorial always blocks 2010-06-21 23:32:30 +02:00
Jan Decaluwe
763ae51960 support for toVerilog.standard, 1995 uses 'or' in sensitivity lists 2010-06-21 22:55:55 +02:00
Jan Decaluwe
115afff6c6 ugly hack to detect orphan else clause for template transformation 2010-06-21 10:48:35 +02:00
Jan Decaluwe
c11f7b9458 fix for if-then-else flattening 2010-06-21 09:14:48 +02:00
Jian Luo
2afac7e7e1 fixed if-elif to case conversion into Verilog 
but conversion into VHDL still fails
 2010-06-20 13:50:29 +02:00
Jan Decaluwe
9799ddb9a9 make sure SIMPLE_ALWAYS_COMB supports lists of signals 2010-06-20 16:54:24 +02:00
Jan Decaluwe
bdeb8c0805 Solved edge inference bug 2010-06-20 14:56:25 +02:00
Jan Decaluwe
34fd26e5a8 changed test to expose edge inference bug 2010-06-20 14:48:35 +02:00
Jan Decaluwe
f32b415dbe additional flag for newer linuxes or gcc's 2010-06-20 13:25:14 +02:00
Jan Decaluwe
58395fb76a error message bug 2010-06-20 13:24:28 +02:00
Jan Decaluwe
83bec53dec smarter prefix handling in hierarchy 2010-06-12 20:17:21 +02:00
Jian Luo
2066201d5d fix a VHDL conversion failure when function has a argument of type 'enum' 2010-06-11 15:38:02 +02:00
Jan Decaluwe
0d7a030e26 Introduced SignalType for instance type checking on Signal objects 2010-06-12 09:45:12 +02:00
Benoit Allard
79a1498e34 Improve Error messages 2009-12-15 18:24:52 +01:00
cfelton@localhost
b8c77379c0 Added a string replace to the intbv constructor for binary strings. It allows the bit separators the same as Verilog. Example x = intbv("0_0000_01010") 2009-10-06 07:02:37 -05:00
cfelton@localhost
0669553305 Added code to determine if a list of signals is used in an alway_comb generator. If so, don't allow the generator to be a SIMPLE_ALWAYS_COMB 2009-09-17 08:37:40 -05:00
Jan Decaluwe
b0aa6536c7 merge from 0.6-maint 2009-07-25 11:07:24 +02:00
Jan Decaluwe
28a0cb90ca Added possibility to yield _Instantiator objects 
--HG--
branch : 0.6-maint
 2009-07-25 09:04:02 +02:00
Jan Decaluwe
18da9ea14e different mapping 2009-06-22 22:52:48 +02:00
Jan Decaluwe
a359a502a0 add conversions to shadow signal examples 2009-06-22 11:25:41 +02:00
Jan Decaluwe
dea2209645 additional shadow signal test example 2009-06-19 22:40:07 +02:00
Jan Decaluwe
65664815cb conversion of shadow signal example 2009-06-19 22:01:45 +02:00
Jan Decaluwe
1e34cf5f36 implmented SliceSignal conversion through slice/index names directly 2009-06-19 12:37:09 +02:00
Jan Decaluwe
5ec4df7ca9 continuous assignments with the Signal.assign() method 2009-06-18 16:02:58 +02:00
Jan Decaluwe
a896ce9bd5 Clean-up shadow signal code, also use attribute instead of type checks 2009-06-18 15:09:09 +02:00
Jan Decaluwe
9c7c09f9cb tristate signal conversion 2009-06-17 22:16:14 +02:00
Jan Decaluwe
7d27594318 TristateSignal as a shadow signal (modeling only) 2009-06-15 18:56:02 +02:00
Jan Decaluwe
01d229db24 ConcatSignal conversion 2009-06-14 09:32:51 +02:00
Jan Decaluwe
56cab73497 ConcatSignal 2009-06-12 00:01:48 +02:00