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33 Commits

Author SHA1 Message Date
Josy Boelen
a9d65c0f87
Class based design (#447)
* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328)  to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default
2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py
This needed the changes of 1) above.

* 1) _Signal.py
added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ...
added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)`
2) _block.py
minor changes
3)_hdlclass.py
removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present
cleaned the code to what is actually working
4) _traceSignals.py
The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting.
So reworked this file to skip adding the None-level
Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice.
Introduce f'strings
5) _analyze.py
changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always
6) test_xxxx.py
changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword

* cleaned test/bugs
replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords

* replacing more occurrences of *logic* by either *comb* or *synch*

* one *comb* too many :(

* added small test_hdlclass0.py to help in debugging
updated the 'doc' section -- needs publishing
added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
2024-12-21 17:21:11 +01:00
Jan Decaluwe
18d0fe0989 Addressed issue #167 2016-05-16 12:30:13 +02:00
Jan Decaluwe
d1fa460311 Update first part of the manual 2016-03-22 18:09:38 +01:00
Jan Decaluwe
f305c9b304 run_sim 2016-03-18 14:48:36 +01:00
Jan Decaluwe
b0e0928ab4 Experiment run method on block 2016-03-13 14:47:52 +01:00
Jan Decaluwe
b13553eefb Rename module -> block 2016-03-12 09:20:20 +01:00
Jan Decaluwe
dad02d8e60 Use module decorator in qualified way 2016-03-10 20:27:07 +01:00
Jan Decaluwe
2961b9ae54 Merge branch 'master' into mep-114
Conflicts:
	myhdl/_Simulation.py
	myhdl/_traceSignals.py
	myhdl/conversion/_toVerilog.py
	myhdl/test/core/test_traceSignals.py
2016-03-05 10:36:21 +01:00
srivatsansoft
8e69e0f334 updated doc for the new public method sim.quit() 2016-03-03 07:46:19 +05:30
Jan Decaluwe
2607e1d525 migrate bitonic 2016-02-03 20:45:26 +01:00
Jan Decaluwe
755d2b8c13 Fix bitonic example; skip locals in AttrRefResolver 2016-02-03 17:24:23 +01:00
Jan Decaluwe
5ad772c4b1 Implemented and documented timescale attribute for VCD output
--HG--
branch : 0.8-dev
2012-04-25 21:25:04 +02:00
Jan Decaluwe
cb05a9b9d2 Removed processes and moved downrange to _misc 2008-08-20 12:21:15 +02:00
jand
393fbc0414 packaged myhdl support functions 2007-06-16 14:44:01 +00:00
jand
045e66ebb8 cookbook examples analyzed 2006-09-19 19:58:18 +00:00
jand
72df2389f0 generated verilog 2006-08-21 22:00:46 +00:00
jand
980fb2ab2d added 2006-08-18 21:13:16 +00:00
jand
fa4c961844 typo 2006-05-11 07:57:27 +00:00
jand
61494f022e info 2006-04-14 09:31:30 +00:00
jand
dd0a217786 page release 2006-04-13 21:04:11 +00:00
jand
10ebc57d47 delete 2006-04-06 20:45:22 +00:00
jand
c98626e4a8 added 2006-04-06 20:40:30 +00:00
jand
a27a85773c improvements 2006-04-06 20:37:44 +00:00
jand
19a5315773 conversion parameters 2006-03-27 21:37:57 +00:00
jand
bc093925be signed handling with righshift
cosimulation bug with signed
2006-03-26 18:55:25 +00:00
jand
f21cf45e1f added 2006-03-24 21:10:18 +00:00
jand
b36111bd42 10Hz clock 2006-03-23 09:31:08 +00:00
jand
6c3e2d832a spaces 2006-03-16 17:49:19 +00:00
jand
189933e6fa commit to svn 2006-03-08 16:03:09 +00:00
jand
1bae62b6b0 remove 2006-02-21 09:25:43 +00:00
jand
47da8e35c5 cookbook 2006-02-21 09:24:55 +00:00
jand
6bf5465d8d slow clk 2006-01-11 17:10:38 +00:00
jand
2bd5eeafde added 2006-01-11 16:21:52 +00:00