FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity
1,595 Commits 9 Branches 41 Tags
Commit Graph

1595 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Jan Decaluwe
3783aebbbb Fix links 2014-08-24 08:44:33 +02:00
Jan Decaluwe
6481ff6caa Merge from default 
--HG--
branch : 0.9-dev
 2014-08-12 16:17:41 +02:00
Jan Decaluwe
95ba19e558 Test name fix 2014-08-12 16:16:58 +02:00
Jan Decaluwe
77de13ac66 Fixed issue #10 (2) 2014-08-12 16:15:21 +02:00
Jan Decaluwe
ff28c3c2d0 Merge from default 
--HG--
branch : 0.9-dev
 2014-08-11 22:42:30 +02:00
Jan Decaluwe
840c858791 Fixed issue #10 2014-08-11 22:40:50 +02:00
Jan Decaluwe
347c20c3fa Fixed issue #8 2014-08-11 21:08:54 +02:00
Jan Decaluwe
740bfdc560 Merge from default 
--HG--
branch : 0.9-dev
 2014-08-03 12:10:55 +02:00
Jan Decaluwe
76896d377b Resolved issue #7 2014-08-03 12:00:43 +02:00
Jan Decaluwe
184090cf45 Merge from default 
--HG--
branch : 0.9-dev
 2014-08-03 09:50:49 +02:00
Jan Decaluwe
40d5ff8770 Switched to rich comparison operators for intbv also 2014-08-03 09:50:11 +02:00
Jan Decaluwe
17eae3d75b Solved issue #9 by introducing rich comparions in the Signal class 2014-08-03 09:20:27 +02:00
Jan Decaluwe
9292680b56 Merged from default 
--HG--
branch : 0.9-dev
 2014-08-02 18:34:05 +02:00
Jan Decaluwe
8fa8387cf1 Fixed bug with boolean constants (reported by Josy Boelen) 2014-08-02 18:33:10 +02:00
Christopher Felton
71be1466de initial doctest commit 2014-05-24 07:43:50 -05:00
Jan Decaluwe
d10fddc9cd merge from default 
--HG--
branch : 0.9-dev
 2014-04-11 18:54:19 +02:00
jandecaluwe
0e268cbf23 Merged in svenstaro/myhdl//fix-docs-this-is-actually-just-3-variabl-1397165148577 (pull request #9) 
Fix docs, this is actually just 3 variables
 2014-04-11 17:14:48 +02:00
Jan Decaluwe
54a6c80af2 Merge PR #8 
--HG--
branch : 0.9-dev
 2014-04-11 17:10:44 +02:00
Jan Decaluwe
ec61ef61e1 merge from default 
--HG--
branch : 0.9-dev
 2014-04-11 15:32:04 +02:00
Jan Decaluwe
8a2526a40c merge from PR #7 2014-04-11 15:31:50 +02:00
Jan Decaluwe
98613a3843 merge pull request #5 
--HG--
branch : 0.9-dev
 2014-04-11 15:27:29 +02:00
Jan Decaluwe
a5bf824555 merge from default 
--HG--
branch : 0.9-dev
 2014-04-11 15:13:55 +02:00
Jan Decaluwe
2c742c425b tabs to spaces 2014-04-11 15:02:50 +02:00
Sven-Hendrik Haase
a57a44f83a Fix docs, this is actually just 3 variables 
--HG--
branch : /fix-docs-this-is-actually-just-3-variabl-1397165148577
 2014-04-10 21:26:05 +00:00
Jan Decaluwe
a975df92ae Fixes for readthedocs 
--HG--
branch : 0.9-dev
 2014-04-08 17:52:21 +02:00
Jan Decaluwe
120537ff0a Fixes for readthedocs 2014-04-08 17:51:37 +02:00
Jan Decaluwe
ff93d83a9e Merge from default 
--HG--
branch : 0.9-dev
 2014-03-17 14:12:33 +01:00
Jan Decaluwe
7f4a2ba1bb Home link position 2014-03-17 14:11:11 +01:00
Jan Decaluwe
2d9833adce Home link position 
--HG--
branch : 0.9-dev
 2014-03-17 14:09:16 +01:00
Jan Decaluwe
1e49af4890 merge from default 
--HG--
branch : 0.9-dev
 2014-03-16 20:29:21 +01:00
Jan Decaluwe
26e361bcf0 moved link 2014-03-16 20:28:44 +01:00
Jan Decaluwe
14469e084e merge from default 
--HG--
branch : 0.9-dev
 2014-03-16 20:25:48 +01:00
Jan Decaluwe
bc782464c9 Link to main site in docs 2014-03-16 20:24:16 +01:00
punkkeks
4124e55a76 When using a tristate-driver as 'local variable' in a device and having a reset function, the init value will be None - that's right so far. But when converting this to verilog (maybe vhdl too) the output will be None, which is wrong, it should be 'bz. 
This should fix it at least for verilog. I think the same thing has to be done for vhdl as well.

--HG--
branch : punkkeks/when-using-a-tristatedriver-as-local-var-1390504597923
 2014-01-23 19:16:55 +00:00
Christopher Felton
85f037f97e new interface conversion test needed prints 
--HG--
branch : 0.9-dev
 2014-01-20 18:32:25 -06:00
Christopher Felton
eec15fc6a2 more interface (MEP107) tests 
--HG--
branch : 0.9-dev
 2013-11-17 19:46:31 -06:00
Keerthan Jaic
eae37779f9 VCD Extension for verilog dumpfile 
--HG--
branch : upstream
 2013-10-24 23:38:25 -04:00
Jan Decaluwe
a8949f771f Merge from default 
--HG--
branch : 0.9-dev
 2013-10-16 22:43:05 +02:00
Jan Decaluwe
a22bb76cc2 Added missing file 2013-10-16 22:42:16 +02:00
Jan Decaluwe
e90995a6ba Updated jck's pull request up to 70f83a 
--HG--
branch : 0.9-dev
 2013-10-16 22:36:39 +02:00
Keerthan Jaic
5af444703e Regression: toVerilog uses the toVerilog.name as module name again 
--HG--
branch : upstream
 2013-10-10 23:53:22 -04:00
Keerthan Jaic
e7f7d31f72 trace support(dumpfile) for toVerilog 
--HG--
branch : upstream
 2013-10-07 01:31:50 -04:00
Keerthan Jaic
755850246c Added portmap attribute to _toVerilog to simplify cosimulation 
--HG--
branch : upstream
 2013-10-06 16:49:35 -04:00
Keerthan Jaic
20211ae5b6 branch representing current upstream state 
--HG--
branch : upstream
 2014-02-07 01:25:22 -05:00
Keerthan Jaic
761d9a95fd improved handling of name conflicts plus unittest 
--HG--
branch : 0.9-dev
 2013-09-29 20:10:50 -04:00
Keerthan Jaic
4f01bf32d4 Signal attr ref names(after replacing . with _) can conflict with memory names 
and vice versa.

--HG--
branch : 0.9-dev
 2013-09-29 18:55:50 -04:00
Jan Decaluwe
a066e18427 Bug fix merge from default 
--HG--
branch : 0.9-dev
 2013-09-22 19:14:21 +02:00
Jan Decaluwe
b6f1e7fd9f Fixed bug 43 2013-09-22 19:13:22 +02:00
Keerthan Jaic
962dd8afcc refeactored repeated code into _makeName 
--HG--
branch : 0.9-dev
 2013-09-21 20:32:19 -04:00
Keerthan Jaic
bad0346b29 prevent unnecesarily adding _ to signal names 
--HG--
branch : 0.9-dev
 2013-09-21 20:28:11 -04:00