Keerthan Jaic
2af83aadba
add python 3.4 to travis
2015-03-11 08:07:34 -04:00
jandecaluwe
6a735cbed5
Merge pull request #26 from jck/travis
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simplify ci.sh
2015-03-11 09:05:47 +01:00
Keerthan Jaic
a8cd14a227
simplify ci.sh
2015-03-11 02:06:00 -04:00
Jan Decaluwe
51766a3c89
Merge branch 'jck-travis'
2015-03-10 22:45:17 +01:00
Jan Decaluwe
f4a6eba227
Merge branch 'travis' of https://github.com/jck/myhdl into jck-travis
2015-03-10 22:42:49 +01:00
Jan Decaluwe
6c2c696af0
Fixed indentation
2015-03-10 22:40:27 +01:00
Josy Boelen
f9ace5d4b7
toVHDL(): added fix when assigning intbv()[1:] to std_logic
2015-03-10 22:33:21 +01:00
jmgc
0c807810c6
Corrected the test_ShadowSignal
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Corrected a minor error that did not take into account that VHDL is not
case sensitive.
2015-03-08 12:33:18 -04:00
Keerthan Jaic
9b3795651d
add GHDL tests to travis
2015-03-03 18:21:57 -05:00
Shen Chen
426dfd8246
pretty print messages during test. exit with nonzero retcode if any test fails.
2015-03-03 18:00:43 -05:00
Jan Decaluwe
094c0e1db7
Fixes so that all tests run
2015-03-03 22:36:10 +01:00
Jan Decaluwe
10040b6941
Cleaned up tests
2015-03-03 21:39:14 +01:00
jandecaluwe
b0acbd2897
Merge pull request #17 from cfelton/master
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added py.test test/core2 to travis
2015-03-03 19:40:12 +01:00
jandecaluwe
0d93c22eef
Update README.md
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Fix badges
2015-03-03 16:22:37 +01:00
Jan Decaluwe
4ddd0d0c93
Merge branch '0.8-maintenance'
2015-03-02 18:28:03 +01:00
Jan Decaluwe
524a2ae95a
Solved github issue #12
2015-03-02 18:27:02 +01:00
Jan Decaluwe
48490359d0
Added gitignore here also
2015-03-02 18:12:37 +01:00
Chris Felton
12d127c1db
added py.test test/core2 to travis
2015-03-01 18:43:57 -06:00
jandecaluwe
88487b8f7a
Merge pull request #16 from javValverde/master
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Change format of README to markdown.
2015-02-28 20:18:12 +01:00
javValverde
e70640328b
Merge branch 'readme'
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Conflicts:
README.md
2015-02-28 19:32:01 +01:00
javValverde
9079c4fe63
Reference @jandecaluwe's travis account
2015-02-28 19:28:49 +01:00
javValverde
1cf1adb3e5
Add landscape badge to README.md
2015-02-28 19:08:36 +01:00
javValverde
6f64189f56
Add 1st version of landscape settings
2015-02-28 19:07:46 +01:00
javValverde
031f88094e
Change format of README to markdown.
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Add badges for docs and build (continuous integration)
2015-02-28 18:53:53 +01:00
jandecaluwe
69c89fa70e
Merge pull request #11 from jck/master
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conv: allow modifying bits of signals inside lists
2015-02-27 08:44:51 +01:00
Keerthan Jaic
da340434e0
conv: allow modifying bits of signals inside lists
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This commit fixes conversion breaking while modifying bits of signal
inside list.
example: somelist[i].next[j] = something
2015-02-26 18:19:09 -08:00
jandecaluwe
cf6f153ced
Merge pull request #8 from cogenda/cosim_cmdline
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Cosim cmdline
2015-02-26 23:32:22 +01:00
jandecaluwe
9de8556f3e
Merge pull request #9 from hgomersall/master
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toVHDL.directory should also set where the package file is placed
2015-02-26 22:51:01 +01:00
jandecaluwe
0eed8f4d61
Merge pull request #7 from jck/master
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Travis CI, gitignore, misc fixes
2015-02-26 22:45:26 +01:00
Keerthan Jaic
e1400e4777
travis: move iverilog installation to travis.yml
2015-02-26 12:04:20 -08:00
Keerthan Jaic
d682d40e31
Merge pull request #1 from cogenda/travis_ci
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travis-ci: add co-simulation tests.
2015-02-26 11:22:59 -08:00
Henry Gomersall
f2049fd860
Merge remote-tracking branch 'upstream/master'
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Merging in upstream master
2015-02-26 12:56:11 +00:00
Henry Gomersall
0945697fc8
Made sure the myhdl VHDL support package is also placed in the desired directory when the directory attribute of toVHDL is set.
2015-02-26 12:52:00 +00:00
Shen Chen
870b735f2b
travis-ci: add co-simulation tests.
2015-02-26 19:39:46 +08:00
Shen Chen
09c98e525e
switch to list-of-command-arguments in cosimulation testcases
2015-02-26 17:53:26 +08:00
Shen Chen
87c6a8a1e3
update docs on Cosimulation(exe, ...)
2015-02-26 17:52:46 +08:00
Shen Chen
f0a98965ba
cosim: simulator command line (exe) may contain arguments with spaces. Use a list of string, each for an argument, in this case.
2015-02-26 16:32:20 +08:00
Keerthan Jaic
ffd01a5eac
remove 'import exceptions'
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It does not need to be imported manually
2015-02-25 20:52:55 -08:00
Keerthan Jaic
2894164a6d
_util.py: remove unused imports
2015-02-25 20:52:36 -08:00
Keerthan Jaic
78eba1bb37
fix _convutils references
2015-02-25 20:52:29 -08:00
Keerthan Jaic
bbeb992115
merge util and convutils
2015-02-25 20:52:12 -08:00
Keerthan Jaic
2c14cefbcb
Fix format string for py2.6 compatibility
2015-02-25 20:52:08 -08:00
Keerthan Jaic
c2021eb8c7
Remove unsupported type check in _analyze.py since it is already done in _toVerilog,_toVHDL
2015-02-25 20:51:53 -08:00
Keerthan Jaic
5d4ebcdf0c
travis: disable email notificatoins
2015-02-25 20:41:56 -08:00
Keerthan Jaic
42e9645ea4
add ci script and travis.yml
2015-02-25 20:32:11 -08:00
Keerthan Jaic
e459c42dd0
Create gitignore
2015-02-25 19:56:56 -08:00
jandecaluwe
a439a92b4d
Merge pull request #4 from josyb/master
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set correct length when initialising an intbv with a binary string containing underscores
2015-02-25 21:00:49 +01:00
Josy Boelen
afd91bdc8d
set correct length when initialising an intbv with a binary string containing underscores
2015-02-25 20:51:30 +01:00
jandecaluwe
912938283d
Merge pull request #3 from cfelton/master
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Updated 0.9 documentation.
2015-02-23 14:13:55 +01:00
Christopher Felton
1513a24e18
Updated 0.9 documentation.
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Updated the MyHDL manual to include the 0.9 what's new in the
index and additional verbage in the conversion section on
interfaces. This commit is also being used as a test vehicle
for the new development flow using git.
2015-02-22 18:52:09 -06:00
