jandecaluwe
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e4b27959d3
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Merge pull request #211 from serpis/fix_traceSignals
Fix signal trace for array-of-enums
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2018-02-23 22:14:14 +01:00 |
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jandecaluwe
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6f80dac0c7
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Merge pull request #189 from hgomersall/improved_block_mk2
[FIX] fixed a couple of issues with the way classes are handled by the new block decorator
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2018-02-23 21:59:39 +01:00 |
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jandecaluwe
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e2dac1c6d0
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Merge pull request #194 from josko7452/josko7452/fix_issue_185
[FIX] Declare signal procedure parameters as signals
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2018-02-23 21:37:56 +01:00 |
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jandecaluwe
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8d18a7a371
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Merge pull request #186 from Vikram9866/issue185
Added test for issue_185
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2018-02-23 21:27:30 +01:00 |
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jandecaluwe
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f66a48c83e
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Merge pull request #188 from josko7452/josko7452/verilog-vhdl-instance-in-block
Add vhdl_/verilog_instance to _Block decorator
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2018-02-23 21:08:40 +01:00 |
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Henry Gomersall
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c6818e2dd9
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Added a blank line to kick travis into rerunning the tests now it has been fixed.
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2018-02-23 13:49:34 +00:00 |
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jandecaluwe
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4553fdd5e7
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Merge pull request #160 from MrCanadianMenace/name_collision_fix
[RDY] Name collision fix (Issue #95)
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2018-02-22 08:43:38 +01:00 |
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Jan Decaluwe
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20e67ff6e5
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devil in detailsss
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2018-02-21 22:21:01 +01:00 |
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Jan Decaluwe
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ab8c802aa1
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try another fix
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2018-02-21 22:07:51 +01:00 |
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Jan Decaluwe
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5abf86d329
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try to fix ghdl path for travis
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2018-02-21 21:34:04 +01:00 |
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jandecaluwe
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212792f98a
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Merge pull request #159 from atharvaw/master
Increasing test coverage for encoding in enum
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2018-02-21 21:00:19 +01:00 |
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Henry Gomersall
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bf3d14a7bb
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Cleaned up the improved block work in order to fix a naming bug on class method blocks.
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2017-11-24 10:32:33 +00:00 |
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Henry Gomersall
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2371c58288
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Merging in upstream changes since original fork.
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2017-11-11 11:56:49 +00:00 |
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jandecaluwe
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29069ae477
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Merge pull request #200 from hgomersall/initial_value_support
[FIX] fixed initial value support for bool lists and list of wires
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2017-04-09 10:20:07 +02:00 |
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jandecaluwe
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1794e952f0
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Merge branch 'master' into initial_value_support
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2017-04-09 10:04:02 +02:00 |
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jandecaluwe
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8ca7a87fbd
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Merge pull request #193 from hgomersall/single_bit_vhdl_representation
[FIX] Tests and fix for VHDL conversion of if/elif/else->case statements for boolean signals
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2017-04-09 09:08:20 +02:00 |
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jandecaluwe
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dc187e244c
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Merge pull request #184 from rqou/multiple_cosim
Remove the limitation to have only one cosimulation
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2017-04-09 09:06:36 +02:00 |
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Keerthan Jaic
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eb4771d280
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Merge pull request #170 from srivatsan-ramesh/master
Added test for issue_169
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2017-03-27 19:04:38 -04:00 |
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Jakob Fries
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48b2ee5f0a
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Fix signal trace for array-of-enums
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2017-01-20 08:53:36 +01:00 |
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Henry Gomersall
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1ef545af9f
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[FIX] Fixed the naming of class method blocks, removing the chance of name collision.
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2017-01-19 17:41:14 +00:00 |
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Keerthan Jaic
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a56544b6e3
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travis: add python 3.6
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2017-01-12 11:23:28 -05:00 |
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Keerthan Jaic
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393c650b0e
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update travis badge in readme
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2016-12-08 16:43:50 -05:00 |
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jandecaluwe
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3736028243
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Update README.md
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2016-11-30 16:28:36 +01:00 |
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Henry Gomersall
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a8a871d520
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[FIX] fixed the initial value case under Verilog where a list of signals are wires.
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2016-11-23 19:04:46 +00:00 |
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jandecaluwe
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1891a2a886
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Merge pull request #197 from jck/travis
Travis improvements
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2016-11-23 18:12:58 +01:00 |
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Henry Gomersall
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5e80435513
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Merge remote-tracking branch 'upstream/master' into initial_value_support
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2016-11-04 16:32:54 +00:00 |
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Henry Gomersall
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498b0b3a52
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FIX: Corrected list of bools initial value support in VHDL.
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2016-11-04 16:27:08 +00:00 |
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Keerthan Jaic
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71f5ff1490
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travis: move simulator installation to before_script
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2016-10-24 23:44:15 -04:00 |
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Keerthan Jaic
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f803c1fd8b
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travis: install simulator only when needed
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2016-10-24 23:38:51 -04:00 |
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Keerthan Jaic
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af2b4cb041
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travis: use new trusty build environment
https://docs.travis-ci.com/user/trusty-ci-environment/
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2016-10-24 23:38:15 -04:00 |
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Keerthan Jaic
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f54ff1a28a
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travis: install ghdl only if CI_TARGET is ghdl
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2016-10-24 23:37:37 -04:00 |
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Keerthan Jaic
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7e25d9dc26
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travis: remove commented out allowed failures
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2016-10-24 23:37:37 -04:00 |
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Bruno Kremel
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23d8fc334f
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Declare signal procedure parameters as signals
To fix issue 185 we need to declare procedure parameters
as signals if they are signals.
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2016-09-06 09:48:19 +02:00 |
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Patrick Egan
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62e1fb9a54
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Fixed object being passed to _nameValidate
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2016-09-02 17:30:38 -04:00 |
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Patrick Egan
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0d6a5d78d0
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made import statement in _toVHDL.py more specific and fixed warning in _VHDLNameValidation
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2016-09-02 15:45:03 -04:00 |
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Patrick Egan
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7f31b570f7
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Fixed _VHDLNameValidation.py method calls in _toVHDL.py
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2016-09-01 23:57:03 -04:00 |
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Patrick Egan
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e11125a07a
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Removed class structure and fixed errors related to .lower() usage
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2016-09-01 12:01:02 -04:00 |
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Patrick Egan
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1520d995c1
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Fixed analyze import problem and updated .gitignore to exclude pycharm configuration files
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2016-09-01 01:51:25 -04:00 |
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Henry Gomersall
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4f8ef24fdf
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[BUGFIX] Tests and fix for VHDL conversion of if/elif/else->case statements for boolean signals
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2016-08-25 16:17:48 +01:00 |
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Henry Gomersall
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ab4a08c3aa
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Fixed problem with setting vhdl_code and verilog_code on class methods and added test.
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2016-08-04 18:37:30 +01:00 |
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Bruno Kremel
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f19f1e3caf
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Add vhdl_/verilog_instance to _Block decorator
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2016-08-04 14:37:02 +02:00 |
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vikram9866
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0ec0cf7e94
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added issue 185
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2016-07-18 18:10:43 +05:30 |
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jandecaluwe
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310abe82ce
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Merge pull request #182 from rqou/fix_print_for_real
Correctly fix _makeAST to preserve future flags
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2016-07-18 07:50:10 +02:00 |
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Robert Ou
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aef94df824
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Remove the limitation to have only one cosimulation
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2016-07-17 17:24:45 -07:00 |
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Robert Ou
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d64ebb4377
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Correctly fix _makeAST to preserve future flags
Examines the actual feature flags in use when compiling the function f
and passes those flags to compile(). Fixes #179.
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2016-07-17 16:00:38 -07:00 |
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Jan Decaluwe
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1761fc2a0e
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Use compile instead of ast.parse() so that future flags can be passed #179
To my suprize, explitly passing the future flags was not required;
apparently the dont_inherit argument is different for ast.parse()
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2016-07-17 17:45:06 +02:00 |
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Jan Decaluwe
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d5501698cc
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Try to get stable results with converts #176
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2016-06-23 19:09:26 +02:00 |
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Jan Decaluwe
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0727f76a9d
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Merge branch 'master' of github.com:jandecaluwe/myhdl
Conflicts:
myhdl/conversion/_toVerilog.py
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2016-06-20 19:13:39 +02:00 |
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Jan Decaluwe
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62675e6a80
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manual update
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2016-06-20 18:59:39 +02:00 |
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jandecaluwe
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f4fde1c9dc
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Merge pull request #150 from hgomersall/initial_value_support
Initial value support
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2016-06-19 21:47:26 +02:00 |
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