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Author SHA1 Message Date
Jan Decaluwe
115afff6c6 ugly hack to detect orphan else clause for template transformation 2010-06-21 10:48:35 +02:00
Jan Decaluwe
c11f7b9458 fix for if-then-else flattening 2010-06-21 09:14:48 +02:00
Jian Luo
2afac7e7e1 fixed if-elif to case conversion into Verilog 
but conversion into VHDL still fails
 2010-06-20 13:50:29 +02:00
Jan Decaluwe
9799ddb9a9 make sure SIMPLE_ALWAYS_COMB supports lists of signals 2010-06-20 16:54:24 +02:00
Jan Decaluwe
bdeb8c0805 Solved edge inference bug 2010-06-20 14:56:25 +02:00
Jan Decaluwe
34fd26e5a8 changed test to expose edge inference bug 2010-06-20 14:48:35 +02:00
Jan Decaluwe
f32b415dbe additional flag for newer linuxes or gcc's 2010-06-20 13:25:14 +02:00
Jan Decaluwe
58395fb76a error message bug 2010-06-20 13:24:28 +02:00
Jan Decaluwe
83bec53dec smarter prefix handling in hierarchy 2010-06-12 20:17:21 +02:00
Jian Luo
2066201d5d fix a VHDL conversion failure when function has a argument of type 'enum' 2010-06-11 15:38:02 +02:00
Jan Decaluwe
0d7a030e26 Introduced SignalType for instance type checking on Signal objects 2010-06-12 09:45:12 +02:00
Benoit Allard
79a1498e34 Improve Error messages 2009-12-15 18:24:52 +01:00
cfelton@localhost
b8c77379c0 Added a string replace to the intbv constructor for binary strings. It allows the bit separators the same as Verilog. Example x = intbv("0_0000_01010") 2009-10-06 07:02:37 -05:00
cfelton@localhost
0669553305 Added code to determine if a list of signals is used in an alway_comb generator. If so, don't allow the generator to be a SIMPLE_ALWAYS_COMB 2009-09-17 08:37:40 -05:00
Jan Decaluwe
b0aa6536c7 merge from 0.6-maint 2009-07-25 11:07:24 +02:00
Jan Decaluwe
28a0cb90ca Added possibility to yield _Instantiator objects 
--HG--
branch : 0.6-maint
 2009-07-25 09:04:02 +02:00
Jan Decaluwe
18da9ea14e different mapping 2009-06-22 22:52:48 +02:00
Jan Decaluwe
a359a502a0 add conversions to shadow signal examples 2009-06-22 11:25:41 +02:00
Jan Decaluwe
dea2209645 additional shadow signal test example 2009-06-19 22:40:07 +02:00
Jan Decaluwe
65664815cb conversion of shadow signal example 2009-06-19 22:01:45 +02:00
Jan Decaluwe
1e34cf5f36 implmented SliceSignal conversion through slice/index names directly 2009-06-19 12:37:09 +02:00
Jan Decaluwe
5ec4df7ca9 continuous assignments with the Signal.assign() method 2009-06-18 16:02:58 +02:00
Jan Decaluwe
a896ce9bd5 Clean-up shadow signal code, also use attribute instead of type checks 2009-06-18 15:09:09 +02:00
Jan Decaluwe
9c7c09f9cb tristate signal conversion 2009-06-17 22:16:14 +02:00
Jan Decaluwe
7d27594318 TristateSignal as a shadow signal (modeling only) 2009-06-15 18:56:02 +02:00
Jan Decaluwe
01d229db24 ConcatSignal conversion 2009-06-14 09:32:51 +02:00
Jan Decaluwe
56cab73497 ConcatSignal 2009-06-12 00:01:48 +02:00
Jan Decaluwe
a0010c904a moved ShadowSignal classes to separate module 2009-06-11 19:18:45 +02:00
Jan Decaluwe
6a280b0767 generalized shadow signal, created _SliceSignal subclass 2009-06-09 18:33:55 +02:00
Jan Decaluwe
cab4c4be8b Turned Signal into a factory function, renamed class to _Signal 2009-06-09 18:07:38 +02:00
Jan Decaluwe
50b2877124 First pass on shadow signals 2009-06-09 17:22:50 +02:00
Jan Decaluwe
3ee96baf1f Merge from 0.6-maint 2009-05-10 08:11:23 +02:00
Jan Decaluwe
8a9ab6cc57 fixed typo 
--HG--
branch : 0.6-maint
 2009-05-10 08:09:10 +02:00
Jan Decaluwe
dc10d0899d COMPLETED - move to ast 
All conversion unit tests work.
 2009-05-09 08:41:59 +02:00
Jan Decaluwe
c1e31def1e UNSTABLE - move to ast 
test_dec.py works
 2009-05-08 21:58:49 +02:00
Jan Decaluwe
7bacfd9c9e UNSTABLE - move to ast 
test_bin2gray works
 2009-05-08 20:22:48 +02:00
Jan Decaluwe
d7c142ad18 UNSTABLE - move to ast 
test_hec.py works for VHDL
 2009-05-04 18:08:57 +02:00
Jan Decaluwe
cad761f30d UNSTABLE - replace compiler by ast 
All unit tests for Verilog conversion work.
 2009-05-03 10:38:52 +02:00
Jan Decaluwe
e6ba8d4ec1 UNSTABLE - replace compiler by ast for conversion 
Tests in conversion/general for Verilog work.
 2009-05-02 22:51:08 +02:00
Jan Decaluwe
c962b8542e UNSTABLE - replace compiler by ast in conversion package 
test_hec.py works for Verilog
 2009-05-02 08:41:32 +02:00
Jan Decaluwe
3d656fd49a Use ast package instead of compiler 2009-04-27 19:26:12 +02:00
Jan Decaluwe
e3cb33b029 Use new standard function for generator function check. 2009-04-26 18:10:37 +02:00
Jan Decaluwe
9e416df6ff Replaced compiler by ast 2009-04-26 18:03:43 +02:00
Jan Decaluwe
cb2ddfb596 merge from 0.6-maint 2009-04-25 21:01:16 +02:00
Jan Decaluwe
2b7f4696de Check for "augmented signal assignemnt" (unsupported). 
This has no semantic equivalence in Verilog/VHDL

--HG--
branch : 0.6-maint
 2009-04-25 20:56:47 +02:00
Jan Decaluwe
fc227fa570 Merge from 0.6-maint 2009-04-25 19:54:17 +02:00
Jan Decaluwe
3cf551cb65 Removed decprecated Set module import. 
On some places, the built-in set type was not yet used

--HG--
branch : 0.6-maint
 2009-04-25 19:49:04 +02:00
Jan Decaluwe
75d85e4b98 setup 0.7dev in default branch 2009-04-25 16:51:01 +02:00
Jan Decaluwe
b2f01c17e0 start 0.6 maintenance branch 
--HG--
branch : 0.6-maint
 2009-04-25 16:47:16 +02:00
Jan Decaluwe
6eb53a6913 Added tag 0.6 for changeset 9e45b91ac223 2009-04-25 16:42:29 +02:00