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Author SHA1 Message Date
Jan Decaluwe
10197ff855 release manifest input rel_0-6dev9 2008-08-24 17:26:12 +02:00
Jan Decaluwe
1697a4fab0 prepare for development release 2008-08-21 15:29:10 +02:00
Jan Decaluwe
9a73012902 Removed tag rel_0-6dev9 2008-08-21 15:12:23 +02:00
Jan Decaluwe
4a7b57096d Added tag rel_0-6dev9 for changeset c5db34e3d223 2008-08-21 15:06:43 +02:00
Jan Decaluwe
f4287e5918 Fix copy of enum items. 
The copy of the initial value of a signal, recently introduced,
created a new enum item object that didn't compare as expected
anymore. The fix is to introduce the special copy methods.
 2008-08-21 15:03:14 +02:00
Jan Decaluwe
f42949c978 Refactored utility and miscellaneous functions 2008-08-20 22:12:10 +02:00
Jan Decaluwe
cb05a9b9d2 Removed processes and moved downrange to _misc 2008-08-20 12:21:15 +02:00
Jan Decaluwe
dfb2fff8e2 Fix _isListOfSignals function 2008-08-02 15:45:28 +02:00
cfelton@localhost
045349965f Added an additional cver makefile for OS X. Also changed the _extracHierachy._isListOfSigs test to "obj is not None" from "obj != None". 2008-07-24 06:29:08 -05:00
cfelton@localhost
bc7b8fc44c Change to the conditional check. The conditional check would error out when numpy arrays were used. Numpy arrays would not resolve to a boolean value when tested. 2008-07-23 21:00:15 -05:00
traber@win.desy.de
4ec1283f1a print with more than one argument does not raise an error anymore but creates a warning. 2008-07-22 14:22:49 +02:00
traber@win.desy.de
4c54ab4b1e print with more than one argument does not raise an error anymore but creates a warning. 2008-07-22 14:14:30 +02:00
thomas.traber@desy.de
40d425d305 Avoid Array Error 2008-07-22 09:48:45 +02:00
Jan Decaluwe
2087bb4778 Test directories documentation 2008-07-21 23:21:18 +02:00
Jan Decaluwe
da825f5fb6 test for ord support 2008-07-11 22:35:20 +02:00
thomas.traber@gmx.net
221d61de03 toVerilog and toVHDL Conversion of builtin function ord() 2008-06-24 10:59:21 +00:00
Jan Decaluwe
525be5c500 Correction to make a 1 bit "signed" intbv possible 2008-06-17 22:31:06 +02:00
Jan Decaluwe
61d779e738 ignore patterns 2008-06-16 20:38:11 +02:00
Jan Decaluwe
6c3947bac2 added sphinx dirs and placeholder files 2008-05-28 14:33:17 +02:00
Jan Decaluwe
1515f3cad8 ignore patterns 2008-05-28 14:28:29 +02:00
Jan Decaluwe
20b398af0a cleaned up keyword expansion 2008-05-28 14:19:37 +02:00
convert-repo
7496bac805 update tags 2008-05-29 06:02:54 +00:00
jand
c4f39dd91e sphinx makefile update 
use palatino font
 2008-04-11 19:56:58 +00:00
jand
146a3fd8aa prune olddoc dir 2008-03-27 16:55:19 +00:00
jand
47fa6fc544 Solved bug related to bit inversion ins expressions 
when converted to VHDL
 2008-03-27 16:52:40 +00:00
jand
773571b2d2 different script name 2008-03-27 16:46:23 +00:00
jand
b36a581e9a added image file (doesn't work with sphinx yet) 2008-03-25 16:01:28 +00:00
jand
d248c2c0b1 rearranged doc layout 2008-03-24 15:45:12 +00:00
jand
8678647c72 added new doc based on sphinx 2008-03-20 20:34:04 +00:00
jand
0464469a03 moved 2008-03-20 20:31:56 +00:00
jand
3203e3ece1 VHDL 2008-03-18 21:13:18 +00:00
jand
0785d56957 corrected path for vpi modules 2008-03-13 16:23:54 +00:00
jand
345fbc636c restructured test dirs 2008-03-13 10:07:21 +00:00
jand
3bb5e57912 rename 2008-03-13 09:56:21 +00:00
jand
d3b5aeba27 Added HDL specific for-loop requirements 
* positive step for Verilog
* unspecified step for VHDL
 2008-03-12 17:15:55 +00:00
jand
9020463980 added tests for general for-loop requirements 
factored those tests out and put in analyzer
 2008-03-12 16:50:43 +00:00
jand
7c4189fd42 Modified bit inversion operation according to newsgroup discussion. 
Added support for bit inversion on signed vars in Verilog
and VHDL conversion
 2008-03-09 14:22:25 +00:00
jand
b1e3b1a1f7 version update 2008-01-30 21:31:38 +00:00
jand
4ead4eeb3d detect variable names that shadow Signal names 2008-01-30 12:56:36 +00:00
jand
a642a95cd7 skip wrongly-placed docstrings 
(was fixed automatically with previous committed fix)
 2008-01-30 09:41:31 +00:00
jand
7e1e3322ed Discard superfluous semicolons in conversion 2008-01-30 09:24:38 +00:00
jand
32f75dd80b support for min and max attribute conversion 2008-01-30 08:53:53 +00:00
jand
12e78c5426 convert constant as argument to int call to int rel_0-6dev6 2008-01-09 16:29:51 +00:00
jand
c87f6f65f3 reset toVerilog attributes after use 2008-01-08 10:05:54 +00:00
jand
e6b9c54c3d improve assert conversion to Verilog 
make sure x-values trigger assertions
 2008-01-07 20:37:24 +00:00
jand
a45c9d4c82 timescale support 2008-01-05 19:37:44 +00:00
jand
c62987ac96 assert conversion to Verilog 
restore _intbv interator as it was before
 2008-01-05 11:40:55 +00:00
jand
c33c631a4b reverse iterator for intbv so indices match with other sequences 
write binary values for intbv's with length > 30
 2008-01-04 21:10:02 +00:00
jand
71f87b37d7 support for Signal read attribute 
convert now() function to VHDL
convert assert statements to VHDL
 2008-01-04 10:22:10 +00:00
jand
a8ee894ddf makefile 2007-12-29 12:55:32 +00:00