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932 Commits

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Author SHA1 Message Date
jand
77a0d8c1d4 conversion bug from IPROBE project 2007-12-20 13:53:23 +00:00
jand
454b2294df inout ports rel_0-6dev5 2007-12-12 15:16:29 +00:00
jand
05192b114d copy initial signal value to avoid issues with mutable types 
introduce unit name in simulator setup templates to solve
case problems with ghdl
 2007-12-05 21:41:30 +00:00
jand
c648715afe support for component declarations 2007-12-02 20:03:32 +00:00
jand
4e89b9458b Add support to remember initial value and 
restore it after a simulation has ended.
This is part of clean-up between simulations
without leaving the interpreter.
 2007-12-02 16:45:48 +00:00
jand
23bf703bfb finally add bound check to bit setting 2007-11-28 20:16:16 +00:00
jand
c8a6cbc65b signal clean-up 2007-11-23 13:35:01 +00:00
jand
35f7e672c6 delay should work with longs 2007-11-23 12:06:45 +00:00
jand
cec118c858 port usage warnings 2007-11-13 20:44:35 +00:00
jand
904e79d824 __vhdl__ 2007-09-04 09:37:05 +00:00
jand
8e6fe737c8 update 2007-07-24 21:01:27 +00:00
jand
ce195a6f51 update 2007-07-23 20:12:56 +00:00
jand
c0ce0463da update 2007-07-23 20:02:14 +00:00
jand
d30bac487d 0.6dev5 setup 2007-06-28 20:45:16 +00:00
jand
90dab3f2dd print 2007-06-28 20:44:37 +00:00
jand
6ce526f179 conversion dir 2007-06-28 20:39:57 +00:00
jand
c8e4a9a86b conversion dir set up 2007-06-28 20:37:15 +00:00
jand
b632bc0bd1 first tests 2007-06-28 20:36:39 +00:00
jand
1ae2c2e9f5 verilog test 2007-06-28 20:34:19 +00:00
jand
8ac1ab0cff sim files 2007-06-25 18:36:30 +00:00
jand
64e602e043 cver, icarus 2007-06-17 19:33:22 +00:00
jand
393fbc0414 packaged myhdl support functions 2007-06-16 14:44:01 +00:00
jand
39a9f76e72 extended print support 2007-06-12 19:07:32 +00:00
jand
f56d526ae0 tristate rename 2007-05-31 18:16:58 +00:00
jand
aff756218a tristate 2007-05-08 14:15:29 +00:00
jand
2004623dd8 experimental tristate support 2007-03-15 21:07:13 +00:00
jand
ffa02c4258 print tests 2007-01-21 21:21:51 +00:00
jand
d2270cdeb7 start of enhanced print support 2007-01-21 20:50:51 +00:00
jand
c60499be92 user defined vhdl code (not instantiations) 2007-01-17 17:05:21 +00:00
jand
9b92962595 move to 0.6dev4 
fix custom Verilog test
 2007-01-12 21:37:43 +00:00
jand
f1056327bd manifest 2006-12-28 10:20:33 +00:00
jand
ad5d1fcf4f File header rel_0-6dev4 2006-12-13 13:11:43 +00:00
jand
636b9678fd finalized signed 2006-12-13 12:55:13 +00:00
jand
10f0c1586a signed operands 
casting
 2006-12-12 15:04:43 +00:00
jand
64c1b26aa6 signed augmented ops 2006-12-07 21:52:21 +00:00
jand
3eb10839bf signed binops 2006-12-07 16:19:33 +00:00
jand
02d7c402d3 binop 2006-12-06 15:33:45 +00:00
jand
cbef36f877 signed binary ops 2006-12-06 14:27:16 +00:00
jand
a0289a4fe8 signed expressions 2006-12-06 09:32:47 +00:00
jand
c7fc9d7633 binary op debug 2006-11-07 13:59:23 +00:00
jand
39a2603d92 augmented assigns 2006-11-07 11:57:26 +00:00
jand
172ff071b4 augmented assigns 2006-10-27 16:17:21 +00:00
jand
2c6c2bf81c augmented assigns - binary 2006-10-27 09:10:58 +00:00
jand
382755425c enum type name rel_0-6dev2 2006-10-13 21:19:31 +00:00
jand
cd72fbb29f ram 2006-10-12 20:32:06 +00:00
jand
f6e94909f7 rom 2006-10-12 15:58:57 +00:00
jand
06e7fa9d06 constants handling 2006-10-10 20:30:50 +00:00
jand
e5d346b79d manifest 2006-10-04 15:28:04 +00:00
jand
81ee5b2159 manifest 2006-10-04 15:21:24 +00:00
jand
bc8aa99816 version number 2006-10-04 15:15:32 +00:00