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• 30cc06686c
  Merge 3caaafaf9fd071b6be22b5782b20f9ae0de930a1 into f0da5a6fa21c867e565187f833049997c1637266 Tanu Hari Dixit 2024-11-22 05:06:01 +00:00
• ebdffc8344
  Merge 12cf3a121b43c5b65fc69413cf0846616c176685 into f0da5a6fa21c867e565187f833049997c1637266 Benjamin Berg 2024-10-24 15:35:57 +02:00
• 706eab0200
  Merge 5bc743a8ad0a9510012e499f613d14be4a9346b5 into f0da5a6fa21c867e565187f833049997c1637266 Nicolas Pinault 2024-10-24 15:35:16 +02:00
• 62c057a528
  Merge 8872249c5696caec1c29375adc5434785e22e437 into f0da5a6fa21c867e565187f833049997c1637266 Dave Keeshan 2024-10-09 11:44:11 +02:00
• e1e0243561
  Merge c027f6f40b25c030ec57b2c4974defbcb99248b2 into f0da5a6fa21c867e565187f833049997c1637266 Josy Boelen 2024-10-09 11:42:26 +02:00
• 91d5e60f8d
  Merge 468b3bf9729ed97548a335cfd08a321851027f99 into f0da5a6fa21c867e565187f833049997c1637266 Stefan Sandström 2024-10-09 11:40:26 +02:00
• 013a383baf
  Merge 2227f1aefdd28d6223be227f15e3c0a2c2625e8e into f0da5a6fa21c867e565187f833049997c1637266 Jos Huisken 2024-10-09 11:38:38 +02:00
• f45ee1121c
  Merge ddcb9d565baa66104c7c597e46ab4d70ec9b2fcc into f0da5a6fa21c867e565187f833049997c1637266 jdavidberger 2024-10-09 11:36:47 +02:00
• ae17d9321a
  Merge f9db0c2bbfa4bc704320289621daf0b757d8fbb8 into f0da5a6fa21c867e565187f833049997c1637266 Jose Ignacio Villar 2024-10-09 11:32:05 +02:00
• a3512f7134
  Merge d88f93ef1b27c2ca9b4dc5a4982f665b525c6149 into f0da5a6fa21c867e565187f833049997c1637266 Zhengfu Li 2024-10-09 11:16:24 +02:00
• f0da5a6fa2
  Fix Icarus cosimulation vpi bug for static signals (#444) master chiplukes 2024-10-05 02:07:42 -06:00
• 4ac4c55554
  Merge branch 'myhdl:master' into master chiplukes 2024-10-04 21:10:39 -06:00
• a9c631f44f
  Merge d925e27d0ac85f7a3b4ba6ff5aa654327ab12145 into 75bb3a7598c6c985441984df9484ca306c8e05ee Nicolas Pinault 2024-10-01 00:00:23 +08:00
• 75bb3a7598
  blocked intialstaion of TristateSignals (#439) Josy Boelen 2024-08-07 20:24:32 +02:00
• 8f50d4e503 blocked intialstaion of TristateSignals Josy 2024-08-07 20:07:46 +02:00
• d0c011d79d
  Update README.md Oleg 2024-07-07 17:21:38 +03:00
• e3b4d5263a
  _toVerilog.py: 'skip_zero_mem_init': repaired test for 'zero' value :( (#433) Josy Boelen 2024-06-14 08:39:27 +02:00
• e66b351fb3 incremented subminor version number Josy 2024-06-14 08:30:37 +02:00
• 1430afa0d4 _toVerilog.py: 'skip_zero_mem_init': repaired test for 'zero' value :( Josy 2024-06-14 08:28:56 +02:00
• ac9b87c273
  _toVerilog.py: 'skip_zero_mem_init': added *forgotten* condition taht the initail value must be zero to be able to skip the genberation of the initial block (#432) Josy Boelen 2024-06-12 10:20:27 +02:00
• 94619802b5 _toVerilog.py: 'skip_zero_mem_init': added *forgotten* condition taht the initail value must be zero to be able to skip the genberation of the initial block Josy 2024-06-12 10:12:19 +02:00
• 6520f32194
  _toVerilog.py: expanding initial_values kwarg to add 'skip_zero_mem_init' choice to skip generating initial block when all values are zero (#431) Josy Boelen 2024-06-11 13:48:35 +02:00
• 3800674265 _toVerilog.py: expanding initial_values kwarg to add 'skip_zero_mem_init' choice to skip generating initial block when all values are zero Josy 2024-06-11 13:26:20 +02:00
• e356d8a589
  Removed support for Python 3.7 (which is End Of Life since 2023-06-27) (#430) Josy Boelen 2024-06-03 11:57:39 +02:00
• b46e5750f5 fix icarus vpi so that all to_myhdl signals are updated at least once even if they are static Chip Lukes 2024-05-13 23:19:59 -06:00
• f76035cd7d created a test that shows the cosimulation bug Chip Lukes 2024-05-11 23:49:29 -06:00
• 43ee357eb1 corrected ord value assignemnt in _toVerilog.py removed forgotten ast.dump call from _analyze.py Josy 2024-02-22 20:15:02 +01:00
• 0b517cca9b corrected import pathj for raises_kind Josy 2024-02-22 19:55:39 +01:00
• 05d275babd Removed support for Python 3.7 (which is End Of Life since 2023-06-27) Removed stray ast.Str and the like , which throw deprecation warnings in Python 3.12 Josy 2024-02-22 19:50:52 +01:00
• 3a7d2f4f8d
  Merge 0b305e64922a774714cfac83e9aecdc984f88e17 into e95762e4efe7077b9e330fc132e69b53c6f81976 Jose Ignacio Villar 2024-02-04 19:26:05 +01:00
• e95762e4ef
  Init list of enums (#428) Josy Boelen 2024-02-04 18:40:30 +01:00
• ac06fa7523 added dedicated test for ListOfSignal(enum) Josy 2024-02-04 18:34:00 +01:00
• e1d1aec29a Merge branch 'master' into init_list_of_enums Josy 2024-02-04 12:22:16 +01:00
• 89365fdf4d correct initial_values for List Of Signal(enum) Josy 2024-02-04 12:10:10 +01:00
• 9f25c072f4
  Change how windows does pip install (#427) Dave Keeshan 2024-02-04 10:07:01 +00:00
• 0511468247 Change how windows does pip install Dave Keeshan 2024-02-03 23:28:16 +00:00
• a0bebbf72d
  corrected .vcd representation for array of enums (#426) Josy Boelen 2024-02-03 13:47:47 +01:00
• c057eacb49 corrected .vcd representation for array of enums corrected pck_myhdl_xx version number, removing the subminor index Josy 2024-02-03 12:52:48 +01:00
• 7cef85c1c6
  **OpenPort** for unused outputs (#424) Josy Boelen 2023-10-19 20:54:26 +02:00
• bc4d1c5f26 Corrected constant array for Verilog 2005 Josy 2023-10-19 20:42:15 +02:00
• beca9ede4b refining detection of OpenPrt in _toVerilog.py Josy 2023-10-19 20:19:59 +02:00
• 32f285ffab Of course we need the new module: _openport.py Josy 2023-10-19 19:49:31 +02:00
• 3034241c09 Added OpenPort to emulate VHDL 'open' port Josy 2023-10-19 19:12:22 +02:00
• 15104a0f8c
  **Constant** signals (#423) Josy Boelen 2023-10-19 17:00:26 +02:00
• a1c3763154 one more *_shortversion* ... Josy 2023-10-19 16:51:59 +02:00
• c8ea8e9c57 Corrected *_shortversion* ToDo: replace by single global variable in myhdl/myhdl/__init__.py Josy 2023-10-19 16:31:23 +02:00
• b61362fcc7 Added Constant signal object Josy 2023-10-19 16:07:47 +02:00
• 4081474f75
  Fix pip install on windows (#422) Dave Keeshan 2023-10-05 07:41:42 -07:00
• e50267da6f Move from python -m pip to just pip Dave Keeshan 2023-10-05 15:21:01 +01:00
• d9f7f10433
  Merge branch 'myhdl:master' into master Dave Keeshan 2023-10-05 06:47:26 -07:00
• 0d51839b1d Patch analyze.py to not mangle toplevel names Thomas Hornschuh 2020-07-20 16:11:05 +02:00
• 7e235fc97a
  doc: added expalantion of how reset opoerates on ListOfSignals (#417) Josy Boelen 2023-04-26 18:07:16 +01:00
• a8c935521a doc: added expalantion of how reset opoerates on ListOfSignals Josy 2023-04-26 18:51:48 +02:00
• ef206f072e
  Cleaning up tests: (#412) Josy Boelen 2023-04-10 13:08:57 +01:00
• c901c0424c some more repairs of new *Vershlimwbesserungen* - literally *improvements that make things worse* :) Josy 2023-04-10 14:00:31 +02:00
• ac64b1bdc7 repaired some over-optimistic "Verschlimmbesserungen" Josy 2023-04-10 13:49:34 +02:00
• 4f8b1df02c
  Updating README.md to show alternative solutions to install MyHDL (#415) Josy Boelen 2023-04-05 13:31:55 +01:00
• 91b8f448f5 editing text Josy 2023-04-05 14:27:46 +02:00
• a8dabc7aa5 adding empty lines after *badges* Josy 2023-04-05 14:26:44 +02:00
• 8fe301e790 trying harder Josy 2023-04-05 14:25:13 +02:00
• a18b9101d7 still reformatting ... Josy 2023-04-05 14:22:37 +02:00
• f6a27224aa reformatting positions of *badges* Josy 2023-04-05 14:21:36 +02:00
• b0c2940fed third try Josy 2023-04-05 14:20:25 +02:00
• e4676406f5 second try to change the image size Josy 2023-04-05 14:12:37 +02:00
• 1e18c91311 trying to make the Discourse a bit smaller Josy 2023-04-05 14:08:02 +02:00
• b692932716 replacing thirdparty Discourse image by original version from Discourse web-site Josy 2023-04-05 14:01:51 +02:00
• 2cfaa46203 getting Discourse image from third-party web-site Josy 2023-04-05 13:58:28 +02:00
• d61087659d removing *stale* link to Travis CI build status; need to find build status of GitHub Actions? updating link to Discourse Josy 2023-04-05 13:40:38 +02:00
• 9b259a4e9f Updating README.md to show alternative solutions to insatll MyHDL instead of installing from the *lagging* PyPI Josy 2023-04-05 13:34:36 +02:00
• 99700a1fb2 replacing for __ inside generator with for dummy cleaning ud 'bugs' section too Josy 2023-03-26 21:34:07 +02:00
• a0c0704855 TestInferWaiter: correct mismatch in number of arguments Josy 2023-03-26 20:35:54 +02:00
• e2c6f83880 Cleaning up tests: removing wildcard imports correcting indents remving as much warnings as possible: mostly unused variables Josy 2023-03-26 20:28:57 +02:00
• 468b3bf972 Reduce memory footprint Stefan Sandstrom 2022-10-08 21:34:30 +02:00
• d835f65e64 Make tests CWD agnostic Stefan Sandstrom 2022-10-08 21:31:37 +02:00
• 5ec3d08d2e
  Add windows actions, python3.11 for core and ghdl (#410) Dave Keeshan 2023-02-08 14:53:35 +00:00
• 2696440a8b Rename some steps to show linux providence Dave Keeshan 2023-02-08 13:42:56 +00:00
• be5b72623f Rename some steps to show linux providence Dave Keeshan 2023-02-08 13:41:16 +00:00
• ed0e7ecd16 Add initial actions for winows, include core and ghdl, iverilog is not working yet Dave Keeshan 2023-02-08 13:39:36 +00:00
• 35bd903371
  True case statment mapping support (#408) Dave Keeshan 2023-02-03 17:08:02 +00:00
• 1dd830fbfc
  Constant value inversion (~0x1, ~0x4523) not working in VHDL (#407) Dave Keeshan 2023-02-03 17:00:11 +00:00
• e0d1f964d4 Rewrite code to be python version dependent, ast.Num was removed in favour of ast.Constant in 3.8 Dave Keeshan 2023-02-03 16:35:10 +00:00
• 3d301eba93 Change ast.Constant to ast.Num, the latter was only introduced in python3.8, it will be deprecated Dave Keeshan 2023-02-03 16:20:38 +00:00
• fc6d6759b9 Ignore the warning as it is a operational message not a testing message Dave Keeshan 2023-02-03 15:48:31 +00:00
• 8e3ef466b6 Rewrite code so that a not int looks like a not int in the VHDL and not the calculated result Dave Keeshan 2023-02-03 15:47:38 +00:00
• 10e749a86c Cleanup of redundant code, and replace some simple variable names with more representative names Dave Keeshan 2023-01-20 23:27:45 +00:00
• 1dddb7b530 Remove unused defs Dave Keeshan 2023-01-20 21:34:34 +00:00
• 7ba40a2a62 Remove unused defs Dave Keeshan 2023-01-20 21:34:31 +00:00
• 9a30069d97 Move appropriate code into match_case definition Dave Keeshan 2023-01-20 21:26:20 +00:00
• 74a42ce4d3 Removed enumerate where not used Dave Keeshan 2023-01-20 21:15:11 +00:00
• 66ca7ecc81 Removed enumerate where not used Dave Keeshan 2023-01-20 21:13:29 +00:00
• 5e27d54c88 Rewrote the code to leverage the correct AST way of walking the case/match tree to build the correct RTL versions Dave Keeshan 2023-01-20 21:10:58 +00:00
• d62cfa9270 Add spport for enumerated types in match statments Dave Keeshan 2023-01-20 16:03:27 +00:00
• 02841c5bf7 Fixed testing so that only the match code is used on python 3.10 or above Dave Keeshan 2023-01-20 12:17:18 +00:00
• 5433477caf Add initial support for match/case in python, only available in 3.10 on Dave Keeshan 2023-01-20 10:52:03 +00:00
• 5461a3d3dc In the cases where the value being inverted is a constant, calculate in the conversion stage the correct inversion value and store that, for a not on a signal name or a boolean there is no change Dave Keeshan 2023-01-19 17:48:38 +00:00
• 16840e29a0 Add test for the inverting of a constant integer (~0x3, ~0x24 etc), this works in myhdl and verilog but fails in VHDL Dave Keeshan 2023-01-19 17:35:36 +00:00
• 0c38f9441b
  Binops convert in VHDL fix (#404) Dave Keeshan 2023-01-19 16:42:54 +00:00
• 52e9efa487 Add dest to rhs signal to allow the destination signal to be rippled along the chain if there are multiple elements/signals being assigned Dave Keeshan 2023-01-19 16:14:58 +00:00
• 4448acb4ad Update tests to find more corner cases Dave Keeshan 2023-01-19 15:42:28 +00:00
• 5dac2a2714 Remove clk from design where it is not used Dave Keeshan 2023-01-19 13:57:24 +00:00