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start

Mono Color

• 6114465ea9 Add tests that shows failing case, in VHDL. When many unsigned, single bit signals are BinOped together (Or'ed in this case) to a boolean (std_logic). Verilog works Dave Keeshan 2023-01-19 13:29:15 +00:00
• 7cdd05c1df Removing Port in List, and Signal in multiple lists Josy 2022-12-29 22:02:47 +01:00
• 9f9a3cd0ab reworking test_issue_122: removing exception test for list in port Josy 2022-12-29 21:52:29 +01:00
• b92f67657a Merge branch 'master' of https://github.com/josyb/myhdl into SystemVerilog Josy 2022-12-29 21:45:07 +01:00
• db1619dadd removed test to detect list of signals as port Josy 2022-12-29 21:29:27 +01:00
• 7c6a5fda54
  Raise traceSignals to DeprecationWarning from UserWarning (#401) Dave Keeshan 2022-12-24 09:48:13 +00:00
• cf29d7cbb0 Raise traceSignals to DeprecationWarning from UserWarning Dave Keeshan 2022-12-23 20:00:40 +00:00
• 9a8f1ee3aa Test Dave Keeshan 2022-12-20 17:38:06 +00:00
• da9adf848a
  Release 0.11.42 (#400) Josy Boelen 2022-12-18 21:17:40 +01:00
• d7b1fce2b5 Release 0.11.42 Josy Boelen 2022-12-18 21:11:43 +01:00
• 3775119f83
  Clean PyPi release flow 17/12/2022 (#399) Dave Keeshan 2022-12-18 19:30:27 +00:00
• bc1127466c Added read definition Dave Keeshan 2022-12-17 21:13:04 +00:00
• 61d43cb39e Add README to release to appear on PyPi Dave Keeshan 2022-12-17 21:09:08 +00:00
• e696be1a73 Add message Dave Keeshan 2022-12-17 20:55:11 +00:00
• c34064318c Add message Dave Keeshan 2022-12-17 20:52:47 +00:00
• 0ca11a5f3c Add message Dave Keeshan 2022-12-17 20:50:43 +00:00
• a20e05e950 Add message Dave Keeshan 2022-12-17 20:49:09 +00:00
• 32cf9486be Add message Dave Keeshan 2022-12-17 20:48:15 +00:00
• 6f966ab538 Add message Dave Keeshan 2022-12-17 20:47:15 +00:00
• 0be2a1b80f Add message Dave Keeshan 2022-12-17 20:46:24 +00:00
• 45c218f549 Add message Dave Keeshan 2022-12-17 20:45:37 +00:00
• 811527ffa4 Add message Dave Keeshan 2022-12-17 20:44:16 +00:00
• 2cce2c6883 Add dist to make and restructure release Dave Keeshan 2022-12-17 20:41:48 +00:00
• c526522b33 Move conditional so the whole job doesn't run unless it is a tag Dave Keeshan 2022-12-17 13:24:26 +00:00
• f8022d3dbd
  Update makeflow (#396) Dave Keeshan 2022-12-17 12:21:08 +00:00
• 555d42181b Add dependancy on tag on push Dave Keeshan 2022-12-16 15:57:05 +00:00
• 462903f4db Update Python versions Dave Keeshan 2022-12-16 15:56:28 +00:00
• 04ac6934a8 Add checkout to step Dave Keeshan 2022-12-16 15:49:16 +00:00
• 064da6299c Update to do a release Dave Keeshan 2022-12-16 15:38:47 +00:00
• f66e43b4aa Fix indent Dave Keeshan 2022-12-16 15:32:27 +00:00
• 7c96f69939 Fix intbv error Dave Keeshan 2022-12-16 15:32:03 +00:00
• 87a26044af Add pypi release steps Dave Keeshan 2022-12-16 15:19:33 +00:00
• 3ca8ead425 Fix pytest to use pytest.ini Dave Keeshan 2022-12-16 15:16:08 +00:00
• fe01fe2eae Fix deprecations catching Dave Keeshan 2022-12-16 15:14:49 +00:00
• e6102938f6 Add more examples for the Deprecation cases, toVHDL and toVerilog Dave Keeshan 2022-12-09 17:16:42 +00:00
• e8f53a10dd Initial checkin with passing flow for new convert VHDL/Verilog, there are a few xfail tests that need to be debugged Dave Keeshan 2022-12-09 17:06:58 +00:00
• c027f6f40b _toVerilog.py: corrected mapToCase conversion of 'test'; replacing integer output by visit(test.comparators[0]) this will properly converts tests like e.g. elif siga == constb // integer: Josy Boelen 2022-12-09 15:40:30 +00:00
• 28aa8af335 Upgrade to DeprecationWarnings Dave Keeshan 2022-12-09 12:56:41 +00:00
• 027b2dc8ce Need to relook at this test, it performs differently for verilog and vhdl Dave Keeshan 2022-12-09 12:37:46 +00:00
• 9197f4471c Add RTL files to the list Dave Keeshan 2022-12-09 12:30:23 +00:00
• f2aeedd935 Need to relook at this test, it performs differently for verilog and vhdl Dave Keeshan 2022-12-09 12:29:55 +00:00
• 481ed7ba9a Remove python2 only testing Dave Keeshan 2022-12-09 12:27:33 +00:00
• 137a0f1081 Add black support Dave Keeshan 2022-12-09 12:18:53 +00:00
• 6c31eeef38 Fix and unmark xfail 2 tests Dave Keeshan 2022-12-09 12:12:45 +00:00
• 90cf810d5d Mark these tests as xfail, for now, Dave Keeshan 2022-12-09 12:00:20 +00:00
• 6e022b3c4c Add myhdl.vpi to clean Dave Keeshan 2022-12-09 11:38:58 +00:00
• 10d92d39c1 The word test is reserved in pytest only for tests, doen't use it for any thing else, like blocks Dave Keeshan 2022-12-09 11:38:36 +00:00
• 48ec4d149e Hide echo commands in window Dave Keeshan 2022-12-09 11:31:51 +00:00
• 8c3f143a3d Add work/ to clean list Dave Keeshan 2022-12-09 11:28:30 +00:00
• 3435c3e3fc Remove matrix step Dave Keeshan 2022-12-09 11:25:57 +00:00
• 96240eb2b4 Add linting step Dave Keeshan 2022-12-09 11:24:13 +00:00
• 0733e2124f Add linting step Dave Keeshan 2022-12-09 11:20:28 +00:00
• f62912f6b5 Add lining step Dave Keeshan 2022-12-09 11:18:56 +00:00
• 0f630298ff Fixed test to look for DeprecationWarning Dave Keeshan 2022-12-09 11:09:02 +00:00
• 13ada8a40c Add some ANSI colored logging Dave Keeshan 2022-12-09 10:58:37 +00:00
• 43bb198f17 No longer use travis Dave Keeshan 2022-12-09 10:41:56 +00:00
• ee3bd13863 Change test operation from script to makefile Dave Keeshan 2022-12-09 10:39:49 +00:00
• 7e5766a4bd Change warning from UserWarning (which is the default) to DeprecationWarning Dave Keeshan 2022-12-09 10:38:00 +00:00
• 37f18d4d97 Add explict test to check for deprecation case Dave Keeshan 2022-12-09 10:36:09 +00:00
• bfaf92f2f4 Add a way to search for and add myhdl.vpi Dave Keeshan 2022-12-09 10:34:42 +00:00
• 0f3fbe7963 Fixed to catch the correct error, List of signals as a port is not supported Dave Keeshan 2022-12-08 17:09:58 +00:00
• 3a9671c0bb Fixed all tests to handle the analyze/verify deprecation Dave Keeshan 2022-12-08 16:38:28 +00:00
• c357c6ebd9 Rewrote test and remove Xfail, test is passing now (is it supposed to fail?) Dave Keeshan 2022-12-08 16:29:47 +00:00
• adec847108 Rewrote test and remove Xfail, test is passing now (is it supposed to fail?) Dave Keeshan 2022-12-08 16:28:46 +00:00
• 72bb13e31d Clean up verify convert warnings Dave Keeshan 2022-12-08 12:51:10 +00:00
• 8872249c56 Fixed inconsistent use of tabs and spaces in indentation Dave Keeshan 2022-12-08 10:07:42 +00:00
• 87122a75f5 Merge branch 'master' into add_reverse Dave Keeshan 2022-12-08 09:59:14 +00:00
• b85c1668c1
  Update flow to compile and used cached version of tools (#387) Dave Keeshan 2022-12-07 13:41:25 +00:00
• 723b726ce4 Update flow to compile and used cached version of tools Dave Keeshan 2022-12-07 10:54:30 +00:00
• d9054d3cb4
  Merge pull request #383 from jtremesay/patch-1 Keerthan Jaic 2022-11-16 05:23:28 +00:00
• 504f46a7dd
  Fix a typo in an error message Jonathan Tremesaygues 2022-11-15 20:22:26 +01:00
• 32c9c7abc1
  add python 3.11 to ci matrix (#382) Keerthan Jaic 2022-11-04 19:39:58 +00:00
• 48a1323741
  add python 3.11 to ci matrix jck-py311 Keerthan Jaic 2022-11-04 05:59:28 +00:00
• fe503496f3 Added conversion for list-port Josy Boelen 2022-11-01 17:09:44 +01:00
• 68f4fe52ee initial support for (true) 'enum' Josy Boelen 2022-10-16 13:13:00 +02:00
• 5b6bdde4f2 Merge branch 'master' into SystemVerilog Josy Boelen 2022-10-16 11:56:08 +02:00
• 279941b8b8
  Added missing visit_NameConnstant() for Python versions 3.7 adn 3.8 (#380) Josy Boelen 2022-10-10 20:12:02 +02:00
• ab52267b1f Added missing visit_NameConnstant() for Python versions 3.7 adn 3.8 Modified test Josy Boelen 2022-10-10 15:07:12 +02:00
• 00496ddb19 _toVerilog: enabled initial_values disregarding 'not _driven' and 'not m._driven == 'wire' Josy Boelen 2022-09-06 09:54:20 +01:00
• 79cf2218f4
  Removed testing with Python 3.6 - EOL <> Added testing with PyPy 3.9 (#376) Josy Boelen 2022-08-02 17:40:09 +02:00
• 00a889d3e5 corrected to 'pypy-3.9' Josy Boelen 2022-08-02 17:34:52 +02:00
• 70c915589a Removed testing with Python 3.6 - EOL Added testing with PyPy 3.9 Josy Boelen 2022-08-02 17:24:12 +02:00
• e6ac73214e
  Conversion with recursive ShadowSignals (#359) Josy Boelen 2022-08-01 18:57:07 +02:00
• 273812a5fc Changed a docstring to launch GitHub actions on origin Josy Boelen 2022-08-01 18:47:40 +02:00
• 1effd72afe added docstring for config_sim() method Josy Boelen 2022-07-31 14:06:35 +02:00
• f19c171b95
  Merge b31219888370c21c61abe8c9b582f885f685a5dd into 0477c7e042aee72fbd2afb722e68f6dee61c102c Luca Sasselli 2022-07-08 09:51:43 +01:00
• 0477c7e042
  [ENH] Updated the ConcatSignal conversion code to check for undriven … (#371) tobygomersall 2022-07-04 18:10:21 +01:00
• 5fc9033adb
  [ENH] Added a test to check the undriven ConcatSignal converts sensibly. Toby Gomersall 2022-07-04 17:49:55 +01:00
• 16e8ccf7b4 Initial support for SystemVerilog: 'logic' where appropriate, ANSI module header, always_comb and always_ff, nicer formatting: proper indenting Josy Boelen 2022-06-18 13:34:15 +02:00
• 4c9337db8d
  [ENH] Updated the ConcatSignal conversion code to check for undriven signals. Toby Gomersall 2022-06-08 14:45:36 +01:00
• 8ad8fac554 wrong startvalue Josy Boelen 2022-05-24 19:39:32 +02:00
• 38098d93a4 added missing returned instance Josy Boelen 2022-05-24 19:35:11 +02:00
• 4701892f24 added test for recursive/chained ShadowSignals Josy Boelen 2022-05-24 19:29:12 +02:00
• ae25af4d59
  Removed 'casez' in Verilog onehot / onecold state encoding (#357) Josy Boelen 2022-05-24 08:21:46 +02:00
• 60dd10aec2 forcing a change to run github actions Josy Boelen 2022-05-24 08:05:27 +02:00
• 212b4b294e
  removed error on reading back outputs of always_comb process (#368) Josy Boelen 2022-04-26 22:06:04 +02:00
• 810c4e086c Merge branch 'readbackoutputs' of https://github.com/josyb/myhdl into readbackoutputs Josy Boelen 2022-04-26 22:01:44 +02:00
• df6bec50ab removed tests for SignalAsInout in AlwaysComb Josy Boelen 2022-04-26 22:01:17 +02:00
• 93dcbd1224
  Update _always_comb.py Josy Boelen 2022-04-26 17:52:26 +02:00
• 0247603e82
  fix typo on structure doc (#365) Rafael Corsi 2022-04-26 12:51:15 -03:00