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start

Mono Color

• ddcb9d565b Added test case for IfExp assigning to an intermediate Justin Berger 2020-02-16 10:21:37 -07:00
• aa1af89c95 Added ability to make a +: operator Justin Berger 2020-01-23 18:49:57 -07:00
• 473d231211 Added test which triggers 'Part select expressions must be constant.' error message Justin Berger 2020-02-16 10:37:56 -07:00
• e605965ad3 Universal wheels are only for when supporting both Python 2 and 3 Hugo 2020-02-04 14:30:37 +02:00
• 0b305e6492 block decorator with parameters and support for simplified signal naming and customizable instance names José Ignacio Villar 2020-01-20 13:56:50 +01:00
• 0a88c20099 first draft of block with parameters José Ignacio Villar 2020-01-20 11:00:38 +01:00
• e60c687b91
  Update README.md Martin 2020-01-12 09:55:48 +01:00
• 870932525f Support for transparent block levels when naming signals hierarchically José Ignacio Villar 2020-01-08 13:31:26 +01:00
• f9db0c2bbf Allow conversion of complex elements in senslists José Ignacio Villar 2020-01-08 13:12:48 +01:00
• eb64accf26 Allow object member signals and kwargs arguments to be used as ports José Ignacio Villar 2020-01-08 13:09:09 +01:00
• 1b0a22fff5
  Merge 58854090bbd434b6bdbb4cde10e01fdb46c90499 into 6c25cb252a9ea5bef36ea82041d26d0285759e80 hashhsah 2019-11-10 14:30:51 -05:00
• 6a8e66aa8c Fix sliceslice code generation Michael Buesch 2019-11-08 22:40:00 +01:00
• 637dfa407b
  Update README.md Martin 2019-11-02 13:10:06 +01:00
• d255e14cde Fixed signed() bounds scenario with addition Martin 2019-10-30 18:18:16 +01:00
• 5a9a69c772 Allow verify() to use additional files Martin 2019-10-30 14:00:03 +01:00
• 84361ff70b
  Update README.md Martin 2019-10-29 12:57:54 +01:00
• 97faae918f
  Added docker notes Martin 2019-10-29 12:54:09 +01:00
• c949a8afe8 First attempt at successful container build Martin 2019-10-29 12:17:17 +01:00
• 471940e2c1 Added preliminary test setup for docker CI Martin 2019-10-29 11:41:44 +01:00
• c339014f71 Made test_resize work with vvp Martin 2019-10-29 09:25:40 +01:00
• 7322a10854 More slice function return support Martin 2019-10-28 20:33:30 +01:00
• 08cd957a3e Converted test_resize to '@block' API Martin 2019-10-28 17:48:50 +01:00
• 5d17a47d0c Merge branch 'upgrade' of https://github.com/hackfin/myhdl into upgrade Martin 2019-10-28 17:19:22 +01:00
• 5be71702d2 More tests passing again with recent GHDL Martin 2019-10-28 17:17:16 +01:00
• 20033bbc61
  Update README.md Martin 2019-10-28 15:10:51 +01:00
• dbbf429d03 Merge branch 'mine' into upgrade Martin 2019-10-28 14:25:33 +01:00
• d61e3ace73 Small extras (conversion to specific VHDL) Martin 2019-10-28 13:02:35 +01:00
• 7bcf43681e Small extras (conversion to specific VHDL) Martin 2019-10-28 13:02:35 +01:00
• ffd71eeef9 Temporary fix to emit correct conversion function Martin 2019-10-27 19:15:58 +01:00
• 88710bda70 Added resize test, eliminate SliceType (python3) Martin 2019-10-27 14:24:42 +01:00
• f5e08cd203 Merge branch 'master' into mine Martin 2019-10-26 00:26:59 +02:00
• 6c25cb252a Updating uart_tx example to use @block decorator and new API. (#320) richmorj 2019-09-15 02:15:56 +01:00
• 127928dd35 Removed unnecessary import myhdl. Rick Richmond 2019-08-24 18:18:50 +01:00
• 461a5bfac2 Removed wildcard import of myhdl. Rick Richmond 2019-08-24 15:48:34 +01:00
• a117714e66 Updating uart_tx example to use @block decorator and new API. Rick Richmond 2019-08-23 22:50:37 +01:00
• 829f6f94ed Function name is fixed (#318) Ahmet Anbar 2019-08-10 23:32:39 +03:00
• 9f38da273a
  Merge branch 'master' into rm-2 Hugo van Kemenade 2019-08-09 13:33:21 +03:00
• 601281ee64 Fix test. NicoPy 2019-08-01 16:04:25 +02:00
• 26dabd3b9d Fix test. NicoPy 2019-08-01 15:59:58 +02:00
• b113079236 Fix test. NicoPy 2019-08-01 15:56:32 +02:00
• 3ef8ced89e Fix test. NicoPy 2019-08-01 15:36:24 +02:00
• 725b919632 Fix bug when converting with toVHDL or toVerilog. NicoPy 2019-08-01 11:42:13 +02:00
• 20438e2139 Enable list in ports. VHDL only. Verilog does not support arrays in ports. NicoPy 2019-08-01 10:53:38 +02:00
• ac29b715a5
  Function name is fixed Ahmet Anbar 2019-07-09 14:03:15 +03:00
• f864f71e9b
  Update _toVHDL.py Joachim Lusiardi 2019-06-06 08:04:48 +02:00
• 5cf68398f1
  Update _toVHDL.py Joachim Lusiardi 2019-06-06 07:39:45 +02:00
• c3a74de25f incremented revision in init 0.11 Christopher Felton 2019-05-31 17:24:04 -05:00
• 22de0e0a84 updated the README to reflect the 0.11 release Christopher Felton 2019-05-31 16:49:39 -05:00
• e3a42a6443
  Updated docs for 0.11 release (#315) Christopher Felton 2019-05-19 15:21:04 -05:00
• 244e285ba1 Merge branch 'master' of https://github.com/myhdl/myhdl into fix-the-docs Christopher Felton 2019-05-19 14:59:19 -05:00
• 2f289f987e
  Merge pull request #297 from myhdl/jck.docs Christopher Felton 2019-05-19 14:58:18 -05:00
• e37ec45008
  Merge pull request #277 from josyb/enum Christopher Felton 2019-05-19 14:57:55 -05:00
• ff91b43065 revert docs back to the myhdl RTD Christopher Felton 2019-05-14 17:04:38 -05:00
• 1bcd6930a4
  Merge pull request #313 from josyb/Doc Christopher Felton 2019-05-12 18:19:11 -05:00
• 4591074572 updated docs for 0.11 release Christopher Felton 2019-05-12 18:12:09 -05:00
• cb84c92d92 (pedantic) correction of deprecated Josy Boelen 2019-05-11 14:50:17 +02:00
• fc89694a11 The future is now Hugo 2019-03-12 18:34:14 +02:00
• 81c76f3a52 Add python_requires to help pip Hugo 2019-03-12 17:57:19 +02:00
• 562aa3a409 Drop support for legacy Python 2.7 Hugo 2019-03-12 17:51:12 +02:00
• a74f26da21 sudo no longer needed https://blog.travis-ci.com/2018-11-19-required-linux-infrastructure-migration Hugo 2019-03-12 15:24:49 +02:00
• f8efa3d041
  Merge pull request #302 from jck/debug_info Keerthan Jaic 2019-02-03 20:15:56 -05:00
• 9374cc6915 add simple debug info module Keerthan Jaic 2019-02-03 17:36:20 -05:00
• ea716db8d2 update installation instructions jck.docs Keerthan Jaic 2019-02-02 22:15:16 -05:00
• e98d663219
  Merge pull request #298 from myhdl/jck.issue_templates Keerthan Jaic 2019-02-02 23:22:13 -05:00
• e25bf37681 basic issue templates Keerthan Jaic 2019-02-02 23:19:18 -05:00
• f696b82ca5
  Merge pull request #275 from rubund/spelling_fixes Christopher Felton 2019-01-09 06:22:30 -06:00
• 56745dc2a5
  Merge pull request #292 from josyb/EKWCD2 Christopher Felton 2019-01-09 06:21:57 -06:00
• 197f1d3c9b Nested Top-Level Interfaces (#270) Josy Boelen 2019-01-09 13:16:52 +01:00
• 8a3af6f856 conversion to VHDL: moved validation of port names before assign port_num names in case of 'std_logic_ports=True' Josy Boelen 2019-01-04 09:21:03 +01:00
• 3e935a074a apparently Verilog doesn't do delta cycles and needs a *real* delay ... Josy Boelen 2018-12-23 10:44:55 +01:00
• c2fede436a added a delta delay between assignment and corresponding print Josy Boelen 2018-12-23 10:09:55 +01:00
• 834ee67ba5 added test for signed ShadowSignal slices Josy Boelen 2018-12-22 21:38:49 +01:00
• 8faa90dfd0 learned that one can not issue a print() statement before all Signals have been assigned to. Else the *external* simulator (ghdl, ...) will print *X* which MyHDL doesn't ... Expanded test_ConcatSignalWithConsts to cover more string variations Josy Boelen 2018-12-22 19:04:04 +01:00
• fb3610ca6e making test/conversion/general/test_ShadowSignal.py close/identical to master branch Josy Boelen 2018-12-22 18:54:35 +01:00
• 523ec1414c searching ... Josy Boelen 2018-12-22 18:28:08 +01:00
• dbd65f5cb7 sometimes one has to think harder ... Josy Boelen 2018-12-22 14:31:10 +01:00
• 431d3b74ef stepping back to check code changes in _ShadowSignal.py only Josy Boelen 2018-12-22 14:14:55 +01:00
• 64a5bf4efd missed one other occurrence of self._args Josy Boelen 2018-12-22 13:28:35 +01:00
• 0d516e4b76 expanded bench_ConcatSignalWithConsts to cover'*extended strings* prettified generated output by *pre-*calculating the x - 1 in the slice expression Josy Boelen 2018-12-22 13:02:04 +01:00
• 2d052b4524 added tests for _IndexSignal and _CloneSignal i _analyze.py added if __name__ = '__main__' section to run conversion test locally Josy Boelen 2018-12-17 21:16:01 +01:00
• 4c9ff98863 (binary?) error search ... Josy Boelen 2018-12-16 19:53:05 +01:00
• e76f7a8d27 *re*: different between 3.x and 2.7? Josy Boelen 2018-12-16 19:36:20 +01:00
• 7c42c12209 typo: tolower() -> lower() Josy Boelen 2018-12-16 19:30:13 +01:00
• 8a285f7ac2 Removed undefined import ReversSignal Josy Boelen 2018-12-16 19:24:41 +01:00
• 20a4e7c39a Enhanced ShadowSignals: Added the possibility to take a ShadowSignal of a whole Signal, which is useful if you e.g. want to build several different ListOfSignals from a pool of Signals. Split the SliceSignal() class over 3 new classes: CLoneSignal, SLiceSignal and IndexSignal to simplify the structure and improve maintainability (and readability) Added a *signed* keyword to allow cutting up a large incoming vector into signed objects. Expanded the allowed string types in ConcatSignal. Josy Boelen 2018-12-16 19:20:14 +01:00
• 6ecadaa658 corrected 'renaming' test_interfaces2.py: added if __name__ == '__main__': section to test locally test_toplevel_interfaces.py: reworked structure Josy Boelen 2018-12-16 13:16:03 +01:00
• 0113c841d9 Merge branch 'master' of https://github.com/myhdl/myhdl into TLI Josy Boelen 2018-12-16 11:39:23 +01:00
• e18557760f Enhanced Enhanced VHDL Keyword Collision Check (#285) Josy Boelen 2018-12-06 15:10:08 +01:00
• 777ecd9679 Replay unsigned fix once again.. Martin 2018-12-06 12:56:21 +01:00
• cbcf27dd48 Merge branch 'TLI' into mine Martin 2018-12-06 12:52:10 +01:00
• b94e67bed0 corrected invalid_function_underscore to call on invalid_signal_underscore to solicit for a double underscore Josy Boelen 2018-12-05 20:12:30 +01:00
• f65826a5a9 move test for used VHDL name one level up added a main i test_keywords.py to run the tests manually (and debug them with print() statements ...) Josy Boelen 2018-12-05 20:04:20 +01:00
• 896e050350 added category=ToVHDLWarning in _nameValid() check Josy Boelen 2018-12-05 19:47:22 +01:00
• 1c074e8e6f corrected (with Henry's help) to run with Python 3.x Josy Boelen 2018-12-05 19:26:21 +01:00
• 43e4190a6a added check for double underscore in VHDL names Josy Boelen 2018-12-05 19:18:42 +01:00
• 286b699032 Merge branch 'vhdl_invalid_names_tests' of https://github.com/hgomersall/myhdl into EKWCD2 Josy Boelen 2018-12-05 17:15:24 +01:00
• bf089ac92a
  [ENH] Added tests for checking the VHDL code for picking up invalid names Henry Gomersall 2018-12-05 15:04:41 +00:00
• 0f5006e430 added clearing of _usednames list at start of conversion Josy Boelen 2018-12-05 13:32:32 +01:00
• db37866574 Temporary commit slice support Martin 2018-12-04 13:15:13 +01:00
• fd286a5b5f Added VHDL Keyword check for 'enum' member names (#271) Josy Boelen 2018-11-13 01:45:56 +01:00