Release 0.4 
-----------

* Conversion to Verilog to provice a path to implementation

For details, consult the whatsnew04.* documents available
in various formats under doc/.

Release 0.3 30-Aug-2003
-----------------------

* VCD output for waveform viewing
* Enumeration types support
* Inferring the sensitivity list for combinatorial logic
* Inferring the list of instances
* Inferring the list of processes
* Class intbv enhancements
* Function concat()
* Python 2.3 support

For details, consult the whatsnew03.* documents available
in various formats under doc/.


Release 0.2 19-May-2003
-----------------------
* Added cosimulation support to MyHDL.
  
A PLI interface module to the Icarus Verilog simulator is included.


Release 0.1 7-Mar-2003
----------------------
* Initial public release