.. currentmodule:: myhdl

.. _new09:

***********************
What's new in MyHDL 0.9
***********************

Python 3 Support
================
Experimental Python 3 support has been added to MyHDL 0.9

See :doc:`/python3` for more info.

Interfaces (Conversion of attribute accesses)
=============================================

Rationale
---------

Complex designs often have many signals that are passed to different levels of
hierarchy.  Typically, many signals logically belong together. This can be
modelled by an *interface*: an object that has a number of :class:`Signal`
objects as its attributes.  Grouping signals into an interface simplifies the
code, improves efficiency, and reduces errors.

The following is an example of an *interface* definition::

    class Complex:
        def __init__(self, min=-2, max=2):
	    self.real = Signal(intbv(0, min=min, max=max))
	    self.imag = Signal(intbv(0, min=min, max=max))


Although previous versions supported interfaces for modeling, they were not 
convertible.  MyHDL 0.9 now supports conversion of designs that use interfaces.

The following is an example using the above ``Complex`` interface definition::

    a,b = Complex(-8,8), Complex(-8,8)
    c = Complex(-128,128)

    def complex_multiply(clock, reset, a, b, c):

        @always_seq(clock.posedge, reset=reset)
        def cmult():
            c.real.next = (a.real*b.real) - (a.imag*b.imag)
	    c.imag.next = (a.real*b.imag) + (a.imag*b.real)

	return cmult
	           

Solution
--------

The proposed solution is to create unique names for attributes which are used
by `MyHDL generator`_\s.  The converter will create a unique name by using the
name of the parent and the name of the attribute along with the name of the
MyHDL module instance. The converter will essentially replace the "." with an
"_" for each interface element. In essence, interfaces are supported
using hierarchical name expansion and name mangling. 

Note that the MyHDL convertor supports interfaces, even though
the target HDLs do not. This is another great example where the
convertor supports a high-level feature that is not available
in the target HDLs.

See also
--------
For additional information see the original proposal `mep-107`_.

.. _mep-107: http://dev.myhdl.org/meps/mep-107.html
.. _MyHDL generator: http://docs.myhdl.org/en/latest/manual/reference.html#myhdl-generators-and-trigger-objects