\documentclass{manual}
\usepackage{palatino}
\renewcommand{\ttdefault}{cmtt}
\renewcommand{\sfdefault}{cmss}
\newcommand{\myhdl}{\protect \mbox{MyHDL}}
\usepackage{graphicx}

\title{The \myhdl\ manual}

\input{boilerplate}

\makeindex

\begin{document}

\maketitle

\input{copyright}

\begin{abstract}

\noindent

\myhdl{} is a Python package for using Python as a hardware description
and verification language. Languages such Verilog and VHDL are
compiled languages. Python with \myhdl{} can be viewed as a "scripting
language" counterpart of such languages. However, Python is more
accurately described as a very high level language (VHLL). \myhdl{} users
have access to the amazing power and elegance of Python.

The key idea behind \myhdl{} is to use Python generators for modeling
hardware concurrency. A generator is a resumable function with
internal state. In \myhdl{}, a hardware module is modeled as a function
that returns generators. With this approach, \myhdl{} directly supports
features such as named port association, arrays of instances, and
conditional instantiation. 

\myhdl{} supports the classic hardware description concepts.  It
provides a signal class similar to the VHDL signal, a class for bit
oriented operations, and support for enumeration types.  The Python
\code{yield} statement is used as a general sensitivity list to wait
on a signal change, an edge, a delay, or on the completion of another
generator. \myhdl{} supports waveform viewing by tracing signal
changes in a VCD file.

Python's rare combination of power and clarity makes it ideal for high
level modeling.  It can be expected that \myhdl{} users will often
have the ``Pythonic experience'' of finding an elegant solution to a
complex modeling problem. Moreover, Python is outstanding for rapid
application development and experimentation.

With \myhdl{}, the Python unit test framework can be used on hardware
designs.  \myhdl{} can also be used as hardware verification language for
VHDL and Verilog designs, by co-simulation with any simulator that has
a PLI.  The distribution contains a PLI module for the
Icarus Verilog simulator.

Finally, a subset of \myhdl{} code can be converted automatically to
synthesizable Verilog code. This feature provides a direct path from
Python to an FPGA or ASIC implementation.

The \myhdl{} software is open source software. It is licensed under the
GNU Lesser General Public License (LGPL).




\end{abstract}

\tableofcontents

\input{background.tex}
\input{informal.tex}
\input{modeling.tex}
\input{unittest.tex}
\input{cosimulation.tex}

\chapter{Conversion to Verilog\label{conv}}
\input{conversion.tex}

\input{reference.tex}

\input{MyHDL.ind}

\end{document}