// File: Inc.v
// Generated by MyHDL 0.6
// Date: Sun Nov 23 11:34:35 2008

`timescale 1ns/10ps

module Inc (
    count,
    enable,
    clock,
    reset
);

output [7:0] count;
reg [7:0] count;
input enable;
input clock;
input reset;




always @(posedge clock, negedge reset) begin: INC_INCLOGIC
    if ((reset == 0)) begin
        count <= 0;
    end
    else begin
        if (enable) begin
            count <= ((count + 1) % 256);
        end
    end
end

endmodule