\documentclass{manual}
\usepackage{palatino}
\renewcommand{\ttdefault}{cmtt}
\renewcommand{\sfdefault}{cmss}
\newcommand{\myhdl}{\protect \mbox{MyHDL}}

\title{The \myhdl\ manual}

\input{boilerplate}

\begin{document}

\maketitle

\input{copyright}

\begin{abstract}

\noindent

\myhdl\ is a Python package for using Python as a hardware description
language. Popular hardware description languages, like Verilog and
VHDL, are compiled languages. Python with \myhdl\ can be viewed as a
"scripting language" counterpart of such languages. However, Python is
more accurately described as a very high level language
(VHLL). \myhdl\ users have access to the amazing power and elegance of
Python for their modeling work.

The key idea behind \myhdl\ is to use Python generators to model the
concurrency required in hardware descriptions. As generators are a
recent Python feature, \myhdl\ requires Python 2.2.2 or higher.

\myhdl\ can be used to experiment with high level modeling, and with
verification techniques such as unit testing. The most important
practical application however, is to use it as a hardware verification
language by co-simulation with Verilog and VHDL.

The present release, \myhdl\ 0.2, enables \myhdl\ for
co-simulation. The \myhdl\ side is designed to work with any simulator
that has a PLI. For each simulator, an appropriate PLI module in C
needs to be provided. The release contains such a module for the
Icarus Verilog simulator.


\end{abstract}

\tableofcontents

\input{background.tex}
\input{informal.tex}
\input{modeling.tex}
\input{unittest.tex}
\input{cosimulation.tex}
\input{reference.tex}

\end{document}
