// File: rom.v
// Generated by MyHDL 0.8dev
// Date: Fri Dec 21 15:02:39 2012


`timescale 1ns/10ps

module rom (
    dout,
    addr
);
// ROM model 

output [7:0] dout;
reg [7:0] dout;
input [3:0] addr;






always @(addr) begin: ROM_READ
    case (addr)
        0: dout = 17;
        1: dout = 134;
        2: dout = 52;
        default: dout = 9;
    endcase
end

endmodule