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f0da5a6fa2
* created a test that shows the cosimulation bug * fix icarus vpi so that all to_myhdl signals are updated at least once even if they are static
14 lines
169 B
Verilog
14 lines
169 B
Verilog
module dut_const_1;
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reg clk;
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wire q;
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initial begin
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$from_myhdl(clk);
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$to_myhdl(q);
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end
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const_1 dut (.q(q), .clk(clk) );
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endmodule // inc
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