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* 1) added J. Villars code from PR#238 (https://github.com/myhdl/myhdl/pull/328) to augment the `@block` decorator with arguments, initially to keep the generated names simpler especially when nesting `block`s without adding *hdl* code - I modified it a bit using `skipname=False` rather than `keepname=True` as default 2) added _hdlclass.py to support Class Based Design, look at bot test/conversion/general/test_hdlclass.py and test/conversion/general/test_hdlclass2.py This needed the changes of 1) above. * 1) _Signal.py added property `.nbits` for use in HDL iso `len(sig)`, anticipating Structure and Array where `len()` is not what `.nbits` will give you ... added `duplicate(value=None)` method to avoid that ugly `newsig = Signal(oldsig._val)` 2) _block.py minor changes 3)_hdlclass.py removed ForwardPorts resolution as this currently adds a *stray* sig in the .vcd output - even if noe ForwardPorts are present cleaned the code to what is actually working 4) _traceSignals.py The `@block(skipname=True), which is heavily used in Class Based Design, applies `None` as that block-name and this will show up as an additional level in the .vcd which looks ugly and distracting. So reworked this file to skip adding the None-level Also added indents in the .vcd var section, primarily for debugging, but kept this as it looks nice. Introduce f'strings 5) _analyze.py changed UPPER_CASE naming of processe/always into lower case, making the generated signals conform with the producing process/always 6) test_xxxx.py changed @instance with *logic* as function name into *comb* as `logic` has become a reserved Verilog keyword * cleaned test/bugs replacing generator names *logic* and *output* with *comb* as `logic` and `output` have become Verilog reserved keywords * replacing more occurrences of *logic* by either *comb* or *synch* * one *comb* too many :( * added small test_hdlclass0.py to help in debugging updated the 'doc' section -- needs publishing added direct conversion of Class Based Design modules - resulting in lesss boiler-plate code
41 lines
1.1 KiB
Python
41 lines
1.1 KiB
Python
import subprocess
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from docutils import nodes
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# deprecated
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# from sphinx.util.compat import Directive
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from docutils.parsers.rst import Directive
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from sphinx.directives.code import LiteralInclude
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example_dir = '/../../example/manual/'
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class IncludeExample(LiteralInclude):
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def run(self):
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self.arguments[0] = '{}/{}'.format(example_dir, self.arguments[0])
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return super(IncludeExample, self).run()
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class RunExample(Directive):
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has_content = False
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required_arguments = 1
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final_argument_whitespace = True
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def run(self):
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document = self.state.document
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env = document.settings.env
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_ , wd = env.relfn2path(example_dir)
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prog = self.arguments[0]
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out = subprocess.check_output(['python', '-u', prog], cwd=wd,
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stderr=subprocess.STDOUT,
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universal_newlines=True)
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out = '$ python {}\n{}'.format(prog, out)
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ret = [nodes.literal_block(out, out)]
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return ret
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def setup(app):
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app.add_directive('include-example', IncludeExample)
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app.add_directive('run-example', RunExample)
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