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27 lines
300 B
Verilog
27 lines
300 B
Verilog
// File: bin2gray.v
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// Generated by MyHDL 1.0dev
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// Date: Mon May 23 16:09:27 2016
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`timescale 1ns/10ps
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module bin2gray (
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B,
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G
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);
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// Gray encoder.
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//
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// B -- binary input
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// G -- Gray encoded output
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input [7:0] B;
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output [7:0] G;
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wire [7:0] G;
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assign G = ((B >>> 1) ^ B);
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endmodule
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