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35 lines
692 B
Python
35 lines
692 B
Python
import myhdl
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from myhdl import *
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def ram(dout, din, addr, we, clk, depth=128):
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""" Ram model """
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mem = [Signal(intbv(0)[8:]) for i in range(depth)]
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@always(clk.posedge)
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def write():
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if we:
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mem[addr].next = din
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@always_comb
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def read():
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dout.next = mem[addr]
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return write, read
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dout = Signal(intbv(0)[8:])
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dout_v = Signal(intbv(0)[8:])
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din = Signal(intbv(0)[8:])
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addr = Signal(intbv(0)[7:])
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we = Signal(bool(0))
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clk = Signal(bool(0))
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def main():
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toVerilog.name = 'ram_1'
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toVerilog(ram, dout, din, addr, we, clk)
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toVHDL(ram, dout, din, addr, we, clk)
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if __name__ == '__main__':
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main()
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