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49 lines
885 B
VHDL
49 lines
885 B
VHDL
-- File: Inc.vhd
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-- Generated by MyHDL 0.8dev
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-- Date: Fri Dec 21 15:02:38 2012
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library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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use std.textio.all;
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use work.pck_myhdl_08.all;
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entity Inc is
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port (
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count: inout unsigned(7 downto 0);
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enable: in std_logic;
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clock: in std_logic;
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reset: in std_logic
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);
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end entity Inc;
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-- Incrementer with enable.
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--
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-- count -- output
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-- enable -- control input, increment when 1
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-- clock -- clock input
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-- reset -- asynchronous reset input
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-- n -- counter max value
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architecture MyHDL of Inc is
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begin
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INC_INCLOGIC: process (clock, reset) is
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begin
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if (reset = '0') then
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count <= (others => '0');
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elsif rising_edge(clock) then
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if bool(enable) then
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count <= (count + 1);
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end if;
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end if;
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end process INC_INCLOGIC;
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end architecture MyHDL;
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