jand fb3b4393bc 0.5

2005-12-27 16:55:12 +00:00

..

_toVerilog

case var name in embedded fsm bug (GP)

2005-12-25 11:37:17 +00:00

experiments

exp

2003-08-07 20:11:42 +00:00

spec

moved here

2003-09-08 19:22:36 +00:00

test

0.5

2005-12-27 14:45:38 +00:00

__init__.py

0.5

2005-12-27 16:55:12 +00:00

_always_comb.py

waiter inference on edge attributes

2005-11-25 09:53:43 +00:00

_always.py

waiter inference on edge attributes

2005-11-25 09:53:43 +00:00

_bin.py

All module names with underscores.

2003-07-24 07:17:46 +00:00

_cell_deref.py

added

2003-12-30 10:48:35 +00:00

_concat.py

isinstance instead of type for type testing

2004-12-07 21:42:49 +00:00

_Cosimulation.py

start signed support

2005-10-06 20:08:36 +00:00

_delay.py

isinstance instead of type for type testing

2004-12-07 21:42:49 +00:00

_enum.py

Introduce base classes EnumType and EnumItemType, for type checking only

2005-11-21 17:03:08 +00:00

_extractHierarchy.py

hierarchical naming simplifying

2005-12-13 16:25:03 +00:00

_instance.py

preparing alpha

2005-11-27 15:42:58 +00:00

_intbv.py

hash

2005-12-19 12:55:24 +00:00

_isGenSeq.py

user-defined verilog

2005-11-13 21:09:42 +00:00

_join.py

error handling

2003-11-18 16:38:22 +00:00

_misc.py

posedge/negedge functions replace by attributes

2005-11-25 15:42:40 +00:00

_Signal.py

hash

2005-12-19 12:55:24 +00:00

_Simulation.py

inference on _always_comb waiters

2005-11-24 14:49:58 +00:00

_simulator.py

lot of progrees on tracing

2003-07-07 21:34:30 +00:00

_traceSignals.py

name attribute

2005-12-22 08:58:00 +00:00

_unparse.py

check for negative intbv's

2004-01-07 17:34:00 +00:00

_util.py

isinstance instead of type for type testing

2004-12-07 21:42:49 +00:00

_Waiter.py

waiter inference on edge attributes

2005-11-25 09:53:43 +00:00