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https://github.com/myhdl/myhdl.git
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119 lines
3.5 KiB
Python
119 lines
3.5 KiB
Python
from math import atan, sqrt, ceil, floor, pi
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from myhdl import *
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t_State = enum("WAITING", "CALCULATING")
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def SineComputer(cos_z0, sin_z0, done, z0, start, clock, reset):
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""" Sine and cosine computer.
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This module computes the sine and cosine of an input angle. The
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floating point numbers are represented as integers by scaling them
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up with a factor corresponding to the number of bits after the point.
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Ports:
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-----
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cos_z0: cosine of the input angle
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sin_z0: sine of the input angle
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done: output flag indicating completion of the computation
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z0: input angle; -pi/2 <= z0 <= pi/2
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start: input that starts the computation on a posedge
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clock: clock input
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reset: reset input
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"""
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# angle input bit width
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W = len(z0)
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# angle input z0 represents number between -pi/2 and pi/2
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# scaling factor corresponds to the nr of bits after the point
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M = 2 ** (W-2)
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# nr of iterations equals nr of significant input bits
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N = W-1
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# calculate X0
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An = 1.0
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for i in range(N):
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An *= (sqrt(1 + 2**(-2*i)))
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# X0
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X0 = int(round(M*1/An))
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# tuple with elementary angles
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angles = tuple([int(round(M*atan(2**(-i)))) for i in range(N)])
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# iterative cordic processor
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@instance
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def processor():
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x = intbv(0, min=sin_z0.min, max=sin_z0.max)
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y = intbv(0, min=sin_z0.min, max=sin_z0.max)
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z = intbv(0, min=z0.min, max=z0.max)
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dx = intbv(0, min=sin_z0.min, max=sin_z0.max)
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dy = intbv(0, min=sin_z0.min, max=sin_z0.max)
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dz = intbv(0, min=z0.min, max=z0.max)
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i = intbv(0, min=0, max=N)
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state = t_State.WAITING
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while True:
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yield clock.posedge, reset.posedge
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if reset:
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state = t_State.WAITING
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cos_z0.next = 1
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sin_z0.next = 0
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done.next = False
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x[:] = 0
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y[:] = 0
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z[:] = 0
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i[:] = 0
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else:
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if state == t_State.WAITING:
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if start:
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x[:] = X0
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y[:] = 0
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z[:] = z0
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i[:] = 0
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done.next = False
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state = t_State.CALCULATING
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elif state == t_State.CALCULATING:
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dx[:] = y >> i
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dy[:] = x >> i
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dz[:] = angles[int(i)]
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if (z >= 0):
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x -= dx
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y += dy
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z -= dz
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else:
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x += dx
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y -= dy
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z += dz
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if i == N-1:
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cos_z0.next = x
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sin_z0.next = y
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state = t_State.WAITING
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done.next = True
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else:
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i += 1
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return processor
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def SineComputer_v(cos_z0, sin_z0, done, z0, start, clock, reset):
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toVerilog(SineComputer, cos_z0, sin_z0, done, z0, start, clock, reset)
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conversion.analyze(SineComputer, cos_z0, sin_z0, done, z0, start, clock, reset)
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cmd = "cver -q +loadvpi=myhdl_vpi:vpi_compat_bootstrap " + \
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"SineComputer.v tb_SineComputer.v"
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return Cosimulation(cmd, **locals())
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## cmd = "iverilog SineComputer.v tb_SineComputer.v"
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## import os
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## os.system(cmd)
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## return Cosimulation("vvp -m ./myhdl.vpi a.out", **locals())
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