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https://github.com/myhdl/myhdl.git
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59 lines
1.0 KiB
Python
59 lines
1.0 KiB
Python
from myhdl import *
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from bin2gray2 import bin2gray
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from inc import Inc
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def GrayInc(graycnt, enable, clock, reset, width):
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bincnt = Signal(modbv(0)[width:])
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inc_1 = Inc(bincnt, enable, clock, reset)
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bin2gray_1 = bin2gray(B=bincnt, G=graycnt, width=width)
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return inc_1, bin2gray_1
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def GrayIncReg(graycnt, enable, clock, reset, width):
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graycnt_comb = Signal(modbv(0)[width:])
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gray_inc_1 = GrayInc(graycnt_comb, enable, clock, reset, width)
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@always(clock.posedge)
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def reg_1():
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graycnt.next = graycnt_comb
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return gray_inc_1, reg_1
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def main():
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width = 8
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graycnt = Signal(modbv(0)[width:])
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enable = Signal(bool())
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clock = Signal(bool())
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reset = ResetSignal(0, active=0, async=True)
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toVerilog(GrayIncReg, graycnt, enable, clock, reset, width)
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toVHDL(GrayIncReg, graycnt, enable, clock, reset, width)
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if __name__ == '__main__':
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main()
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